From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, yijun@loongson.cn,
shenjinyang@loongson.cn, Jiajie Chen <c@jia.je>,
Song Gao <gaosong@loongson.cn>,
Xiaojuan Yang <yangxiaojuan@loongson.cn>
Subject: [PATCH v3 4/6] target/loongarch: Support LoongArch32 TLB entry
Date: Mon, 7 Aug 2023 17:45:03 +0800 [thread overview]
Message-ID: <20230807094505.2030603-5-c@jia.je> (raw)
In-Reply-To: <20230807094505.2030603-1-c@jia.je>
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu-csr.h | 9 +++++----
target/loongarch/tlb_helper.c | 17 ++++++++++++-----
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index f8f24032cb..48ed2e0632 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
FIELD(TLBENTRY, PLV, 2, 2)
FIELD(TLBENTRY, MAT, 4, 2)
FIELD(TLBENTRY, G, 6, 1)
-FIELD(TLBENTRY, PPN, 12, 36)
-FIELD(TLBENTRY, NR, 61, 1)
-FIELD(TLBENTRY, NX, 62, 1)
-FIELD(TLBENTRY, RPLV, 63, 1)
+FIELD(TLBENTRY_32, PPN, 8, 24)
+FIELD(TLBENTRY_64, PPN, 12, 36)
+FIELD(TLBENTRY_64, NR, 61, 1)
+FIELD(TLBENTRY_64, NX, 62, 1)
+FIELD(TLBENTRY_64, RPLV, 63, 1)
#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
FIELD(CSR_ASID, ASID, 0, 10)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 6e00190547..690c6ef25f 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
- tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
- tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
- tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
- tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+ if (env->mode == LA64) {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+ tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+ tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+ tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+ } else {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+ tlb_nx = 0;
+ tlb_nr = 0;
+ tlb_rplv = 0;
+ }
/* Check access rights */
if (!tlb_v) {
@@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
* tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
* need adjust.
*/
- *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+ *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
(address & MAKE_64BIT_MASK(0, tlb_ps));
*prot = PAGE_READ;
if (tlb_d) {
--
2.39.2
next prev parent reply other threads:[~2023-08-07 9:46 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-07 9:44 [PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu Jiajie Chen
2023-08-07 9:45 ` [PATCH v3 1/6] target/loongarch: " Jiajie Chen
2023-08-07 15:13 ` Richard Henderson
2023-08-07 15:14 ` Jiajie Chen
2023-08-07 9:45 ` [PATCH v3 2/6] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
2023-08-07 9:54 ` WANG Xuerui
2023-08-07 9:55 ` Jiajie Chen
2023-08-07 15:17 ` Richard Henderson
2023-08-07 9:45 ` [PATCH v3 3/6] target/loongarch: Add GDB support for loongarch32 mode Jiajie Chen
2023-08-07 15:19 ` Richard Henderson
2023-08-07 9:45 ` Jiajie Chen [this message]
2023-08-07 15:41 ` [PATCH v3 4/6] target/loongarch: Support LoongArch32 TLB entry Richard Henderson
2023-08-07 9:45 ` [PATCH v3 5/6] target/loongarch: Support LoongArch32 DMW Jiajie Chen
2023-08-07 15:50 ` Richard Henderson
2023-08-07 17:32 ` Jiajie Chen
2023-08-07 19:34 ` Richard Henderson
2023-08-07 9:45 ` [PATCH v3 6/6] target/loongarch: Support LoongArch32 VPPN Jiajie Chen
2023-08-07 9:48 ` Jiajie Chen
2023-08-07 11:53 ` gaosong
2023-08-07 11:56 ` Jiajie Chen
2023-08-07 15:40 ` [PATCH v3 0/6] Add loongarch32 mode for loongarch64-softmmu Richard Henderson
2023-08-07 15:43 ` Jiajie Chen
2023-08-07 15:56 ` Richard Henderson
2023-08-07 15:58 ` Jiajie Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230807094505.2030603-5-c@jia.je \
--to=c@jia.je \
--cc=gaosong@loongson.cn \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=shenjinyang@loongson.cn \
--cc=yangxiaojuan@loongson.cn \
--cc=yijun@loongson.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).