From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, yijun@loongson.cn,
shenjinyang@loongson.cn, gaosong@loongson.cn, i.qemu@xen0n.name,
Jiajie Chen <c@jia.je>, Xiaojuan Yang <yangxiaojuan@loongson.cn>
Subject: [PATCH v5 01/11] target/loongarch: Add function to check current arch
Date: Wed, 9 Aug 2023 16:26:29 +0800 [thread overview]
Message-ID: <20230809083258.1787464-2-c@jia.je> (raw)
In-Reply-To: <20230809083258.1787464-1-c@jia.je>
Add is_la64 function to check if the current cpucfg[1].arch equals to
2(LA64).
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..5a71d64a04 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -132,6 +132,11 @@ FIELD(CPUCFG1, HP, 24, 1)
FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
FIELD(CPUCFG1, MSG_INT, 26, 1)
+/* cpucfg[1].arch */
+#define CPUCFG1_ARCH_LA32R 0
+#define CPUCFG1_ARCH_LA32 1
+#define CPUCFG1_ARCH_LA64 2
+
/* cpucfg[2] bits */
FIELD(CPUCFG2, FP, 0, 1)
FIELD(CPUCFG2, FP_SP, 1, 1)
@@ -420,6 +425,11 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#endif
}
+static inline bool is_la64(CPULoongArchState *env)
+{
+ return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
+}
+
/*
* LoongArch CPUs hardware flags.
*/
--
2.41.0
next prev parent reply other threads:[~2023-08-09 8:33 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-09 8:26 [PATCH v5 00/11] Add la32 & va32 support for loongarch64-softmmu Jiajie Chen
2023-08-09 8:26 ` Jiajie Chen [this message]
2023-08-09 8:26 ` [PATCH v5 02/11] target/loongarch: Add new object class for loongarch32 cpus Jiajie Chen
2023-08-09 14:47 ` Richard Henderson
2023-08-09 8:26 ` [PATCH v5 03/11] target/loongarch: Add GDB support for loongarch32 mode Jiajie Chen
2023-08-09 8:26 ` [PATCH v5 04/11] target/loongarch: Support LoongArch32 TLB entry Jiajie Chen
2023-08-09 8:26 ` [PATCH v5 05/11] target/loongarch: Support LoongArch32 DMW Jiajie Chen
2023-08-09 8:26 ` [PATCH v5 06/11] target/loongarch: Support LoongArch32 VPPN Jiajie Chen
2023-08-09 8:26 ` [PATCH v5 07/11] target/loongarch: Add LA64 & VA32 to DisasContext Jiajie Chen
2023-08-09 8:26 ` [PATCH v5 08/11] target/loongarch: Reject la64-only instructions in la32 mode Jiajie Chen
2023-08-09 15:03 ` Richard Henderson
2023-08-10 2:38 ` gaosong
2023-08-10 2:58 ` Richard Henderson
2023-08-11 8:12 ` gaosong
2023-08-11 15:18 ` Richard Henderson
2023-08-14 8:59 ` gaosong
2023-08-09 8:26 ` [PATCH v5 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode Jiajie Chen
2023-08-09 15:10 ` Richard Henderson
2023-08-09 8:26 ` [PATCH v5 10/11] target/loongarch: Sign extend results " Jiajie Chen
2023-08-09 15:11 ` Richard Henderson
2023-08-09 8:26 ` [PATCH v5 11/11] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
2023-08-09 15:11 ` Richard Henderson
2023-08-10 12:47 ` gaosong
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