From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 2/5] target/arm: Reduce dcz_blocksize to uint8_t
Date: Wed, 9 Aug 2023 19:35:45 -0700 [thread overview]
Message-ID: <20230810023548.412310-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org>
This value is only 4 bits wide.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 88e5accda6..7fedbb34ba 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1074,7 +1074,8 @@ struct ArchCPU {
bool prop_lpa2;
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
- uint32_t dcz_blocksize;
+ uint8_t dcz_blocksize;
+
uint64_t rvbar_prop; /* Property/input signals. */
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
--
2.34.1
next prev parent reply other threads:[~2023-08-10 2:37 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-10 2:35 [PATCH for-8.2 0/5] target/arm: Implement cortex-a710 Richard Henderson
2023-08-10 2:35 ` [PATCH 1/5] target/arm: Disable FEAT_TRF in neoverse-v1 Richard Henderson
2023-08-10 9:16 ` Peter Maydell
2023-08-10 2:35 ` Richard Henderson [this message]
2023-08-10 14:09 ` [PATCH 2/5] target/arm: Reduce dcz_blocksize to uint8_t Peter Maydell
2023-08-10 19:02 ` Richard Henderson
2023-08-10 2:35 ` [PATCH 3/5] target/arm: Allow cpu to configure GM blocksize Richard Henderson
2023-08-10 14:13 ` Peter Maydell
2023-08-10 2:35 ` [PATCH 4/5] target/arm: Support more GM blocksizes Richard Henderson
2023-08-10 14:23 ` Peter Maydell
2023-08-10 19:10 ` Richard Henderson
2023-08-10 2:35 ` [PATCH 5/5] target/arm: Implement cortex-a710 Richard Henderson
2023-08-10 4:11 ` Richard Henderson
2023-08-10 15:49 ` Peter Maydell
2023-08-10 17:05 ` Richard Henderson
2023-08-10 17:12 ` Peter Maydell
2023-08-14 8:49 ` Marcin Juszkiewicz
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