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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id a9-20020a5d5089000000b0031434c08bb7sm4669985wrt.105.2023.08.11.01.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 01:25:53 -0700 (PDT) Date: Fri, 11 Aug 2023 10:25:52 +0200 From: Andrew Jones To: Palmer Dabbelt Cc: rbagley@ventanamicro.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis , bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com Subject: Re: [PATCH] disas/riscv: Further correction to LUI disassembly Message-ID: <20230811-bc15b48d336b79d9ec1f0936@orel> References: <20230810-c9e1f2783168b48bc07a1aa2@orel> <20230810-e160f9edae60ded9d2606b8b@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230810-e160f9edae60ded9d2606b8b@orel> Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 10, 2023 at 06:27:50PM +0200, Andrew Jones wrote: > On Thu, Aug 10, 2023 at 09:12:42AM -0700, Palmer Dabbelt wrote: > > On Thu, 10 Aug 2023 08:31:46 PDT (-0700), ajones@ventanamicro.com wrote: > > > On Mon, Jul 31, 2023 at 11:33:20AM -0700, Richard Bagley wrote: > > > > The recent commit 36df75a0a9 corrected one aspect of LUI disassembly > > > > by recovering the immediate argument from the result of LUI with a > > > > shift right by 12. However, the shift right will left-fill with the > > > > sign. By applying a mask we recover an unsigned representation of the > > > > 20-bit field (which includes a sign bit). > > > > > > > > Example: > > > > 0xfffff000 >> 12 = 0xffffffff > > > > 0xfffff000 >> 12 & 0xfffff = 0x000fffff > > > > > > > > Fixes: 36df75a0a9 ("riscv/disas: Fix disas output of upper immediates") > > > > Signed-off-by: Richard Bagley > > > > --- > > > > disas/riscv.c | 9 ++++++--- > > > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/disas/riscv.c b/disas/riscv.c > > > > index 4023e3fc65..690eb4a1ac 100644 > > > > --- a/disas/riscv.c > > > > +++ b/disas/riscv.c > > > > @@ -4723,9 +4723,12 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) > > > > break; > > > > case 'U': > > > > fmt++; > > > > - snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12); > > > > - append(buf, tmp, buflen); > > > > - if (*fmt == 'o') { > > > > + if (*fmt == 'i') { > > > > + snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12 & 0xfffff); > > > > > > Why are we correcting LUI's output, but still outputting sign-extended > > > values for AUIPC? > > > > > > We can't assemble 'auipc a1, 0xffffffff' or 'auipc a1, -1' without getting > > > > > > Error: lui expression not in range 0..1048575 > > > > > > (and additionally for 0xffffffff) > > > > > > Error: value of 00000ffffffff000 too large for field of 4 bytes at 0000000000000000 > > > > > > either. > > > > > > (I see that the assembler's error messages state 'lui', but I was trying > > > 'auipc'.) > > > > > > I'm using as from gnu binutils 2.40.0.20230214. > > > > > > (And, FWIW, I agree with Richard Henderson that these instructions should > > > accept negative values.) > > > > I'm kind of lost here, and you saying binutils rejects this syntax? If > > that's the case it's probably just an oversight, can you file a bug in > > binutils land so folks can see? > > Will do. > https://sourceware.org/bugzilla/show_bug.cgi?id=30746 Thanks, drew