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Tsirkin" To: Guoyi Tu Cc: Marcel Apfelbaum , qemu-devel@nongnu.org, =?utf-8?B?6KKB5piO5rWp?= Subject: Re: pci: Fix the update of interrupt disable bit in PCI_COMMAND register Message-ID: <20230811120936-mutt-send-email-mst@kernel.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 11, 2023 at 10:46:51PM +0800, Guoyi Tu wrote: > The PCI_COMMAND register is located at offset 4 within > the PCI configuration space and occupies 2 bytes. The > interrupt disable bit is at the 10th bit, which corresponds > to the byte at offset 5 in the PCI configuration space. > > In our testing environment, the guest driver may directly > updates the byte at offset 5 in the PCI configuration space. > The backtrace looks like as following: > #0 pci_default_write_config (d=0x5580bbfc6230, addr=5, val_in=5, l=1) > at hw/pci/pci.c:1442 > #1 0x00005580b8f3156a in virtio_write_config (pci_dev=0x5580bbfc6230, > address=5, val=5, len=1) > at hw/virtio/virtio-pci.c:605 > #2 0x00005580b8ed2f3b in pci_host_config_write_common > (pci_dev=0x5580bbfc6230, addr=5, limit=256, > val=5, len=1) at hw/pci/pci_host.c:81 > > In this situation, the range_covers_byte function called > by the pci_default_write_config function will return false, > resulting in the inability to handle the interrupt disable > update event. > > To fix this issue, we can use the ranges_overlap function > instead of range_covers_byte to determine whether the interrupt > bit has been updated. > > Signed-off-by: Guoyi Tu > Signed-off-by: yuanminghao Oh wow good catch! Fixes: b6981cb57be5 ("pci: interrupt disable bit support") clearly stable material too. > --- > hw/pci/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > index b8d22e2e74..881d774fb6 100644 > --- a/hw/pci/pci.c > +++ b/hw/pci/pci.c > @@ -1613,7 +1613,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t > addr, uint32_t val_in, int > range_covers_byte(addr, l, PCI_COMMAND)) > pci_update_mappings(d); > > - if (range_covers_byte(addr, l, PCI_COMMAND)) { > + if (ranges_overlap(addr, l, PCI_COMMAND, 2)) { > pci_update_irq_disabled(d, was_irq_disabled); > memory_region_set_enabled(&d->bus_master_enable_region, > (pci_get_word(d->config + PCI_COMMAND) > -- > 2.27.0 > > -- > Guoyi