From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, jniethe5@gmail.com
Subject: [PATCH v3 05/14] tcg/ppc: Use ADDPCIS in tcg_out_tb_start
Date: Tue, 15 Aug 2023 12:57:32 -0700 [thread overview]
Message-ID: <20230815195741.8325-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230815195741.8325-1-richard.henderson@linaro.org>
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIP.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 19004fa568..36b4f61236 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -362,6 +362,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define CRNAND XO19(225)
#define CROR XO19(449)
#define CRNOR XO19( 33)
+#define ADDPCIS XO19( 2)
#define EXTSB XO31(954)
#define EXTSH XO31(922)
@@ -854,6 +855,19 @@ static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
}
+static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm)
+{
+ int d0, d1, d2;
+
+ tcg_debug_assert((imm & 0xffff) == 0);
+ tcg_debug_assert(imm == (int32_t)imm);
+
+ d2 = imm & 1;
+ d1 = (imm >> 1) & 0x1f;
+ d0 = (imm >> 6) & 0x3ff;
+ tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2);
+}
+
static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
@@ -2489,9 +2503,14 @@ static void tcg_out_tb_start(TCGContext *s)
{
/* Load TCG_REG_TB. */
if (USE_REG_TB) {
- /* bcl 20,31,$+4 (preferred form for getting nia) */
- tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK);
- tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
+ if (have_isa_3_00) {
+ /* lnia REG_TB */
+ tcg_out_addpcis(s, TCG_REG_TB, 0);
+ } else {
+ /* bcl 20,31,$+4 (preferred form for getting nia) */
+ tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK);
+ tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
+ }
}
}
--
2.34.1
next prev parent reply other threads:[~2023-08-15 19:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-15 19:57 [PATCH v3 00/14] tcg/ppc: direct branching, power9, power10 Richard Henderson
2023-08-15 19:57 ` [PATCH v3 01/14] tcg/ppc: Untabify tcg-target.c.inc Richard Henderson
2023-08-15 19:57 ` [PATCH v3 02/14] tcg: Add tcg_out_tb_start backend hook Richard Henderson
2023-08-15 19:57 ` [PATCH v3 03/14] tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB Richard Henderson
2023-08-15 19:57 ` [PATCH v3 04/14] tcg/ppc: Reinterpret tb-relative to TB+4 Richard Henderson
2023-08-15 19:57 ` Richard Henderson [this message]
2023-08-23 9:39 ` [PATCH v3 05/14] tcg/ppc: Use ADDPCIS in tcg_out_tb_start Jordan Niethe
2023-08-23 17:10 ` Richard Henderson
2023-08-15 19:57 ` [PATCH v3 06/14] tcg/ppc: Use ADDPCIS in tcg_out_movi_int Richard Henderson
2023-08-15 19:57 ` [PATCH v3 07/14] tcg/ppc: Use ADDPCIS for the constant pool Richard Henderson
2023-08-15 19:57 ` [PATCH v3 08/14] tcg/ppc: Use ADDPCIS in tcg_out_goto_tb Richard Henderson
2023-08-15 19:57 ` [PATCH v3 09/14] tcg/ppc: Use PADDI in tcg_out_movi Richard Henderson
2023-08-15 19:57 ` [PATCH v3 10/14] tcg/ppc: Use prefixed instructions in tcg_out_mem_long Richard Henderson
2023-08-15 19:57 ` [PATCH v3 11/14] tcg/ppc: Use PLD in tcg_out_movi for constant pool Richard Henderson
2023-08-15 19:57 ` [PATCH v3 12/14] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec Richard Henderson
2023-08-15 19:57 ` [PATCH v3 13/14] tcg/ppc: Use PLD in tcg_out_goto_tb Richard Henderson
2023-08-15 19:57 ` [PATCH v3 14/14] RFC tcg/ppc: Disable TCG_REG_TB for Power9/Power10 Richard Henderson
2023-09-15 4:19 ` Jordan Niethe
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