From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org, Song Gao <gaosong@loongson.cn>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>,
Huacai Chen <chenhuacai@loongson.cn>, Jiajie Chen <c@jia.je>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN
Date: Tue, 22 Aug 2023 09:13:49 +0200 [thread overview]
Message-ID: <20230822071405.35386-4-philmd@linaro.org> (raw)
In-Reply-To: <20230822071405.35386-1-philmd@linaro.org>
From: Jiajie Chen <c@jia.je>
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-4-gaosong@loongson.cn>
---
target/loongarch/cpu-csr.h | 6 ++++--
target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index b93f99a9ef..c59d7a9fcb 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6)
FIELD(CSR_TLBIDX, NE, 31, 1)
#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
-FIELD(CSR_TLBEHI, VPPN, 13, 35)
+FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
+FIELD(CSR_TLBEHI_64, VPPN, 13, 35)
#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
@@ -164,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62)
#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
FIELD(CSR_TLBREHI, PS, 0, 6)
-FIELD(CSR_TLBREHI, VPPN, 13, 35)
+FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
+FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
FIELD(CSR_TLBRPRMD, PIE, 2, 1)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 1f8e7911c7..c8b8b0497f 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -300,8 +300,13 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
if (tlb_error == TLBRET_NOMATCH) {
env->CSR_TLBRBADV = address;
- env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
- extract64(address, 13, 35));
+ if (is_la64(env)) {
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
+ VPPN, extract64(address, 13, 35));
+ } else {
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
+ VPPN, extract64(address, 13, 19));
+ }
} else {
if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
env->CSR_BADV = address;
@@ -366,12 +371,20 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
- csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
+ if (is_la64(env)) {
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
+ } else {
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
+ }
lo0 = env->CSR_TLBRELO0;
lo1 = env->CSR_TLBRELO1;
} else {
csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
- csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
+ if (is_la64(env)) {
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
+ } else {
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
+ }
lo0 = env->CSR_TLBELO0;
lo1 = env->CSR_TLBELO1;
}
@@ -491,7 +504,7 @@ void helper_tlbfill(CPULoongArchState *env)
if (pagesize == stlb_ps) {
/* Only write into STLB bits [47:13] */
- address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
+ address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
/* Choose one set ramdomly */
set = get_random_tlb(0, 7);
--
2.41.0
next prev parent reply other threads:[~2023-08-22 7:16 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-22 7:13 [PATCH RESEND v5 00/19] Add some checks before translating instructions Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 01/19] target/loongarch: Support LoongArch32 TLB entry Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 02/19] target/loongarch: Support LoongArch32 DMW Philippe Mathieu-Daudé
2023-08-22 7:13 ` Philippe Mathieu-Daudé [this message]
2023-08-22 7:13 ` [PATCH RESEND v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 05/19] target/loongarch: Extract make_address_x() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 06/19] target/loongarch: Extract make_address_i() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 07/19] target/loongarch: Extract make_address_pc() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 08/19] target/loongarch: Extract set_pc() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 10/19] target/loongarch: Sign extend results " Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 11/19] target/loongarch: Add a check parameter to the TRANS macro Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 12/19] target/loongarch: Add avail_64 to check la64-only instructions Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132 Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 14/19] hw/loongarch: Remove restriction of la464 cores in the virt machine Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 15/19] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 17/19] target/loongarch: Add avail_LAM to check atomic instructions Philippe Mathieu-Daudé
2023-08-22 7:22 ` [PATCH RESEND v5 19/19] target/loongarch: Add avail_IOCSR to check iocsr instructions Philippe Mathieu-Daudé
2023-08-22 7:30 ` [PATCH RESEND v5 18/19] target/loongarch: Add avail_LSX to check LSX instructions Philippe Mathieu-Daudé
2023-08-22 8:21 ` [PATCH RESEND v5 00/19] Add some checks before translating instructions gaosong
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