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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org, Song Gao <gaosong@loongson.cn>
Cc: "Xiaojuan Yang" <yangxiaojuan@loongson.cn>,
	"Huacai Chen" <chenhuacai@loongson.cn>, "Jiajie Chen" <c@jia.je>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH RESEND v5 07/19] target/loongarch: Extract make_address_pc() helper
Date: Tue, 22 Aug 2023 09:13:53 +0200	[thread overview]
Message-ID: <20230822071405.35386-8-philmd@linaro.org> (raw)
In-Reply-To: <20230822071405.35386-1-philmd@linaro.org>

From: Jiajie Chen <c@jia.je>

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/translate.c                   | 5 +++++
 target/loongarch/insn_trans/trans_arith.c.inc  | 2 +-
 target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index acc54d7587..8b26555a27 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -226,6 +226,11 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
     return make_address_x(ctx, base, addend);
 }
 
+static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
+{
+    return addr;
+}
+
 #include "decode-insns.c.inc"
 #include "insn_trans/trans_arith.c.inc"
 #include "insn_trans/trans_shift.c.inc"
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
index 43d6cf261d..2aea4e41d5 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -72,7 +72,7 @@ static bool gen_pc(DisasContext *ctx, arg_r_i *a,
                    target_ulong (*func)(target_ulong, int))
 {
     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
-    target_ulong addr = func(ctx->base.pc_next, a->imm);
+    target_ulong addr = make_address_pc(ctx, func(ctx->base.pc_next, a->imm));
 
     tcg_gen_movi_tl(dest, addr);
     gen_set_gpr(a->rd, dest, EXT_NONE);
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
index 3ad34bcc05..2e35572cea 100644
--- a/target/loongarch/insn_trans/trans_branch.c.inc
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -12,7 +12,7 @@ static bool trans_b(DisasContext *ctx, arg_b *a)
 
 static bool trans_bl(DisasContext *ctx, arg_bl *a)
 {
-    tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+    tcg_gen_movi_tl(cpu_gpr[1], make_address_pc(ctx, ctx->base.pc_next + 4));
     gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
@@ -25,7 +25,7 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
 
     TCGv addr = make_address_i(ctx, src1, a->imm);
     tcg_gen_mov_tl(cpu_pc, addr);
-    tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+    tcg_gen_movi_tl(dest, make_address_pc(ctx, ctx->base.pc_next + 4));
     gen_set_gpr(a->rd, dest, EXT_NONE);
     tcg_gen_lookup_and_goto_ptr();
     ctx->base.is_jmp = DISAS_NORETURN;
-- 
2.41.0



  parent reply	other threads:[~2023-08-22  7:15 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-22  7:13 [PATCH RESEND v5 00/19] Add some checks before translating instructions Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 01/19] target/loongarch: Support LoongArch32 TLB entry Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 02/19] target/loongarch: Support LoongArch32 DMW Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 05/19] target/loongarch: Extract make_address_x() helper Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 06/19] target/loongarch: Extract make_address_i() helper Philippe Mathieu-Daudé
2023-08-22  7:13 ` Philippe Mathieu-Daudé [this message]
2023-08-22  7:13 ` [PATCH RESEND v5 08/19] target/loongarch: Extract set_pc() helper Philippe Mathieu-Daudé
2023-08-22  7:13 ` [PATCH RESEND v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 10/19] target/loongarch: Sign extend results " Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 11/19] target/loongarch: Add a check parameter to the TRANS macro Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 12/19] target/loongarch: Add avail_64 to check la64-only instructions Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132 Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 14/19] hw/loongarch: Remove restriction of la464 cores in the virt machine Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 15/19] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions Philippe Mathieu-Daudé
2023-08-22  7:19 ` [PATCH RESEND v5 17/19] target/loongarch: Add avail_LAM to check atomic instructions Philippe Mathieu-Daudé
2023-08-22  7:22 ` [PATCH RESEND v5 19/19] target/loongarch: Add avail_IOCSR to check iocsr instructions Philippe Mathieu-Daudé
2023-08-22  7:30 ` [PATCH RESEND v5 18/19] target/loongarch: Add avail_LSX to check LSX instructions Philippe Mathieu-Daudé
2023-08-22  8:21 ` [PATCH RESEND v5 00/19] Add some checks before translating instructions gaosong

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