[PATCH RESEND v5 10/19] target/loongarch: Sign extend results in VA32 mode

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

From: Jiajie Chen <c@jia.je>

In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
---
 target/loongarch/translate.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 9a23ec786d..de7c1c5d1f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -238,6 +238,9 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
 
 static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
 {
+    if (ctx->va32) {
+        addr = (int32_t)addr;
+    }
     return addr;
 }
 
-- 
2.41.0