From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org, Song Gao <gaosong@loongson.cn>
Cc: Jiajie Chen <c@jia.je>, Xiaojuan Yang <yangxiaojuan@loongson.cn>,
Huacai Chen <chenhuacai@loongson.cn>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH RESEND v5 19/19] target/loongarch: Add avail_IOCSR to check iocsr instructions
Date: Tue, 22 Aug 2023 09:22:19 +0200 [thread overview]
Message-ID: <20230822072219.35719-1-philmd@linaro.org> (raw)
In-Reply-To: <20230822071405.35386-1-philmd@linaro.org>
From: Song Gao <gaosong@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-16-gaosong@loongson.cn>
---
target/loongarch/translate.h | 2 +-
.../loongarch/insn_trans/trans_privileged.c.inc | 16 ++++++++--------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index db46e9aa0f..89b49a859e 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -23,7 +23,7 @@
#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
-
+#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
index 099cd871f0..4cb701b4b5 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -312,14 +312,14 @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a,
return true;
}
-TRANS(iocsrrd_b, ALL, gen_iocsrrd, gen_helper_iocsrrd_b)
-TRANS(iocsrrd_h, ALL, gen_iocsrrd, gen_helper_iocsrrd_h)
-TRANS(iocsrrd_w, ALL, gen_iocsrrd, gen_helper_iocsrrd_w)
-TRANS(iocsrrd_d, ALL, gen_iocsrrd, gen_helper_iocsrrd_d)
-TRANS(iocsrwr_b, ALL, gen_iocsrwr, gen_helper_iocsrwr_b)
-TRANS(iocsrwr_h, ALL, gen_iocsrwr, gen_helper_iocsrwr_h)
-TRANS(iocsrwr_w, ALL, gen_iocsrwr, gen_helper_iocsrwr_w)
-TRANS(iocsrwr_d, ALL, gen_iocsrwr, gen_helper_iocsrwr_d)
+TRANS(iocsrrd_b, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_b)
+TRANS(iocsrrd_h, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_h)
+TRANS(iocsrrd_w, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_w)
+TRANS(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d)
+TRANS(iocsrwr_b, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_b)
+TRANS(iocsrwr_h, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_h)
+TRANS(iocsrwr_w, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_w)
+TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
static void check_mmu_idx(DisasContext *ctx)
{
--
2.41.0
next prev parent reply other threads:[~2023-08-22 7:22 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-22 7:13 [PATCH RESEND v5 00/19] Add some checks before translating instructions Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 01/19] target/loongarch: Support LoongArch32 TLB entry Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 02/19] target/loongarch: Support LoongArch32 DMW Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 05/19] target/loongarch: Extract make_address_x() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 06/19] target/loongarch: Extract make_address_i() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 07/19] target/loongarch: Extract make_address_pc() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 08/19] target/loongarch: Extract set_pc() helper Philippe Mathieu-Daudé
2023-08-22 7:13 ` [PATCH RESEND v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 10/19] target/loongarch: Sign extend results " Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 11/19] target/loongarch: Add a check parameter to the TRANS macro Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 12/19] target/loongarch: Add avail_64 to check la64-only instructions Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132 Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 14/19] hw/loongarch: Remove restriction of la464 cores in the virt machine Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 15/19] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions Philippe Mathieu-Daudé
2023-08-22 7:19 ` [PATCH RESEND v5 17/19] target/loongarch: Add avail_LAM to check atomic instructions Philippe Mathieu-Daudé
2023-08-22 7:22 ` Philippe Mathieu-Daudé [this message]
2023-08-22 7:30 ` [PATCH RESEND v5 18/19] target/loongarch: Add avail_LSX to check LSX instructions Philippe Mathieu-Daudé
2023-08-22 8:21 ` [PATCH RESEND v5 00/19] Add some checks before translating instructions gaosong
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