From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: [PULL 31/48] tcg/sparc64: Implement negsetcond_*
Date: Wed, 23 Aug 2023 13:23:09 -0700 [thread overview]
Message-ID: <20230823202326.1353645-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230823202326.1353645-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc64/tcg-target.h | 4 ++--
tcg/sparc64/tcg-target.c.inc | 40 +++++++++++++++++++++++++++---------
2 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
index 79889db760..3d41c9659b 100644
--- a/tcg/sparc64/tcg-target.h
+++ b/tcg/sparc64/tcg-target.h
@@ -106,7 +106,7 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_negsetcond_i32 0
+#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
@@ -143,7 +143,7 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
-#define TCG_TARGET_HAS_negsetcond_i64 0
+#define TCG_TARGET_HAS_negsetcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index ffcb879211..f2a346a1bd 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -720,7 +720,7 @@ static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
}
static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, int32_t c2, int c2const)
+ TCGReg c1, int32_t c2, int c2const, bool neg)
{
/* For 32-bit comparisons, we can play games with ADDC/SUBC. */
switch (cond) {
@@ -760,22 +760,34 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
default:
tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movi_s13(s, ret, 0);
- tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
+ tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1);
return;
}
tcg_out_cmp(s, c1, c2, c2const);
if (cond == TCG_COND_LTU) {
- tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
+ if (neg) {
+ /* 0 - 0 - C = -C = (C ? -1 : 0) */
+ tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC);
+ } else {
+ /* 0 + 0 + C = C = (C ? 1 : 0) */
+ tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
+ }
} else {
- tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
+ if (neg) {
+ /* 0 + -1 + C = C - 1 = (C ? 0 : -1) */
+ tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC);
+ } else {
+ /* 0 - -1 - C = 1 - C = (C ? 0 : 1) */
+ tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
+ }
}
}
static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, int32_t c2, int c2const)
+ TCGReg c1, int32_t c2, int c2const, bool neg)
{
- if (use_vis3_instructions) {
+ if (use_vis3_instructions && !neg) {
switch (cond) {
case TCG_COND_NE:
if (c2 != 0) {
@@ -796,11 +808,11 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
if the input does not overlap the output. */
if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
tcg_out_movi_s13(s, ret, 0);
- tcg_out_movr(s, cond, ret, c1, 1, 1);
+ tcg_out_movr(s, cond, ret, c1, neg ? -1 : 1, 1);
} else {
tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movi_s13(s, ret, 0);
- tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1);
}
}
@@ -1355,7 +1367,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
break;
case INDEX_op_setcond_i32:
- tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
+ tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, false);
+ break;
+ case INDEX_op_negsetcond_i32:
+ tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, true);
break;
case INDEX_op_movcond_i32:
tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
@@ -1437,7 +1452,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
break;
case INDEX_op_setcond_i64:
- tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
+ tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, false);
+ break;
+ case INDEX_op_negsetcond_i64:
+ tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, true);
break;
case INDEX_op_movcond_i64:
tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
@@ -1564,6 +1582,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_sar_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
+ case INDEX_op_negsetcond_i32:
+ case INDEX_op_negsetcond_i64:
return C_O1_I2(r, rZ, rJ);
case INDEX_op_brcond_i32:
--
2.34.1
next prev parent reply other threads:[~2023-08-23 20:25 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 20:22 [PULL 00/48] tcg patch queue Richard Henderson
2023-08-23 20:22 ` [PULL 01/48] accel/kvm: Widen pc/saved_insn for kvm_sw_breakpoint Richard Henderson
2023-08-23 20:22 ` [PULL 02/48] accel/hvf: Widen pc/saved_insn for hvf_sw_breakpoint Richard Henderson
2023-08-23 20:22 ` [PULL 03/48] sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint Richard Henderson
2023-08-23 20:22 ` [PULL 04/48] sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpoint Richard Henderson
2023-08-23 20:22 ` [PULL 05/48] include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*() Richard Henderson
2023-08-23 20:22 ` [PULL 06/48] include/exec: typedef abi_ptr to vaddr in softmmu Richard Henderson
2023-08-23 20:22 ` [PULL 07/48] include/exec: Widen tlb_hit/tlb_hit_page() Richard Henderson
2023-08-23 20:22 ` [PULL 08/48] accel/tcg: Widen address arg in tlb_compare_set() Richard Henderson
2023-08-23 20:22 ` [PULL 09/48] accel/tcg: Update run_on_cpu_data static assert Richard Henderson
2023-08-23 20:22 ` [PULL 10/48] target/m68k: Use tcg_gen_deposit_i32 in gen_partset_reg Richard Henderson
2023-08-23 20:22 ` [PULL 11/48] tcg/i386: Drop BYTEH deposits for 64-bit Richard Henderson
2023-08-23 20:22 ` [PULL 12/48] tcg: Fold deposit with zero to and Richard Henderson
2023-08-23 20:22 ` [PULL 13/48] tcg/i386: Allow immediate as input to deposit_* Richard Henderson
2023-08-23 20:22 ` [PULL 14/48] docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32() Richard Henderson
2023-08-23 20:22 ` [PULL 15/48] tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32 Richard Henderson
2023-08-23 20:22 ` [PULL 16/48] tcg: Introduce negsetcond opcodes Richard Henderson
2023-08-23 20:22 ` [PULL 17/48] tcg: Use tcg_gen_negsetcond_* Richard Henderson
2023-08-23 20:22 ` [PULL 18/48] target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero Richard Henderson
2023-08-23 20:22 ` [PULL 19/48] target/arm: Use tcg_gen_negsetcond_* Richard Henderson
2023-08-23 20:22 ` [PULL 20/48] target/m68k: " Richard Henderson
2023-08-23 20:22 ` [PULL 21/48] target/openrisc: " Richard Henderson
2023-08-23 20:23 ` [PULL 22/48] target/ppc: " Richard Henderson
2023-08-23 20:23 ` [PULL 23/48] target/sparc: Use tcg_gen_movcond_i64 in gen_edge Richard Henderson
2023-08-23 20:23 ` [PULL 24/48] target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl Richard Henderson
2023-08-23 20:23 ` [PULL 25/48] tcg/ppc: Implement negsetcond_* Richard Henderson
2023-08-23 20:23 ` [PULL 26/48] tcg/ppc: Use the Set Boolean Extension Richard Henderson
2023-08-23 20:23 ` [PULL 27/48] tcg/aarch64: Implement negsetcond_* Richard Henderson
2023-08-23 20:23 ` [PULL 28/48] tcg/arm: Implement negsetcond_i32 Richard Henderson
2023-08-23 20:23 ` [PULL 29/48] tcg/riscv: Implement negsetcond_* Richard Henderson
2023-08-23 20:23 ` [PULL 30/48] tcg/s390x: " Richard Henderson
2023-08-23 20:23 ` Richard Henderson [this message]
2023-08-23 20:23 ` [PULL 32/48] tcg/i386: Merge tcg_out_brcond{32,64} Richard Henderson
2023-08-23 20:23 ` [PULL 33/48] tcg/i386: Merge tcg_out_setcond{32,64} Richard Henderson
2023-08-23 20:23 ` [PULL 34/48] tcg/i386: Merge tcg_out_movcond{32,64} Richard Henderson
2023-08-23 20:23 ` [PULL 35/48] tcg/i386: Use CMP+SBB in tcg_out_setcond Richard Henderson
2023-08-23 20:23 ` [PULL 36/48] tcg/i386: Clear dest first in tcg_out_setcond if possible Richard Henderson
2023-08-23 20:23 ` [PULL 37/48] tcg/i386: Use shift in tcg_out_setcond Richard Henderson
2023-08-23 20:23 ` [PULL 38/48] tcg/i386: Implement negsetcond_* Richard Henderson
2023-08-23 20:23 ` [PULL 39/48] tcg/tcg-op: Document bswap16_i32() byte pattern Richard Henderson
2023-08-23 20:23 ` [PULL 40/48] tcg/tcg-op: Document bswap16_i64() " Richard Henderson
2023-08-23 20:23 ` [PULL 41/48] tcg/tcg-op: Document bswap32_i32() " Richard Henderson
2023-08-23 20:23 ` [PULL 42/48] tcg/tcg-op: Document bswap32_i64() " Richard Henderson
2023-08-23 20:23 ` [PULL 43/48] tcg/tcg-op: Document bswap64_i64() " Richard Henderson
2023-08-23 20:23 ` [PULL 44/48] tcg/tcg-op: Document hswap_i32/64() " Richard Henderson
2023-08-23 20:23 ` [PULL 45/48] tcg/tcg-op: Document wswap_i64() " Richard Henderson
2023-08-23 20:23 ` [PULL 46/48] target/cris: Fix a typo in gen_swapr() Richard Henderson
2023-08-23 20:23 ` [PULL 47/48] docs/devel/tcg-ops: fix missing newlines in "Host vector operations" Richard Henderson
2023-08-23 20:23 ` [PULL 48/48] tcg: spelling fixes Richard Henderson
2023-08-24 14:05 ` [PULL 00/48] tcg patch queue Stefan Hajnoczi
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