* [PATCH] target/i386/tcg: Check for valid descriptor table before loading segment descriptor
@ 2023-08-24 10:46 Rayhan Faizel
0 siblings, 0 replies; only message in thread
From: Rayhan Faizel @ 2023-08-24 10:46 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, richard.henderson, eduardo, Rayhan Faizel
LSL and LAR can cause segmentation faults in certain scenarios under QEMU.
This occurs particularly when the base of either GDT or LDT depending on
bit 2 of selector is NULL.
On real CPU, invalid LSL/LAR does nothing besides clearing ZF.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1376
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
---
target/i386/tcg/seg_helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index e8d19c65fd..4c36462162 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -78,6 +78,10 @@ static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr,
} else {
dt = &env->gdt;
}
+ /* Check valid DT base before fetching segment descriptor*/
+ if (!dt->base) {
+ return -1;
+ }
index = selector & ~7;
if ((index + 7) > dt->limit) {
return -1;
--
2.41.0
^ permalink raw reply related [flat|nested] only message in thread
only message in thread, other threads:[~2023-08-24 13:15 UTC | newest]
Thread overview: (only message) (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-24 10:46 [PATCH] target/i386/tcg: Check for valid descriptor table before loading segment descriptor Rayhan Faizel
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).