From: deller@kernel.org
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
Helge Deller <deller@gmx.de>
Subject: [PATCH v2 3/5] target/hppa: Do not use hardcoded value for tlb_flush_*()
Date: Fri, 25 Aug 2023 08:56:36 +0200 [thread overview]
Message-ID: <20230825065638.7262-4-deller@kernel.org> (raw)
In-Reply-To: <20230825065638.7262-1-deller@kernel.org>
From: Helge Deller <deller@gmx.de>
Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/hppa/cpu.h | 5 +++++
target/hppa/helper.c | 2 +-
target/hppa/mem_helper.c | 7 +++----
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 50b513f0ea..6623712644 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -41,6 +41,11 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* No need to flush MMU_PHYS_IDX */
+#define HPPA_MMU_FLUSH_MASK \
+ (1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX | \
+ 1 << MMU_PL2_IDX | 1 << MMU_USER_IDX)
+
/* Hardware exceptions, interrupts, faults, and traps. */
#define EXCP_HPMC 1 /* high priority machine check */
#define EXCP_POWER_FAIL 2
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 74b8747083..a8d3f456ee 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -71,7 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
/* If PSW_P changes, it affects how we translate addresses. */
if ((psw ^ old_psw) & PSW_P) {
#ifndef CONFIG_USER_ONLY
- tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
#endif
}
}
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 5046cc8f9d..6f04c101dd 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -50,8 +50,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
- /* Do not flush MMU_PHYS_IDX. */
- tlb_flush_page_by_mmuidx(cs, addr, 0xf);
+ tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK);
}
memset(ent, 0, sizeof(*ent));
@@ -335,13 +334,13 @@ void HELPER(ptlbe)(CPUHPPAState *env)
{
trace_hppa_tlb_ptlbe(env);
memset(env->tlb, 0, sizeof(env->tlb));
- tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
}
void cpu_hppa_change_prot_id(CPUHPPAState *env)
{
if (env->psw & PSW_P) {
- tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
}
}
--
2.41.0
next prev parent reply other threads:[~2023-08-25 6:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 6:56 [PATCH v2 0/5] target/hppa: Clean up conversion from/to MMU index and privilege level deller
2023-08-25 6:56 ` [PATCH v2 1/5] target/hppa: Add missing PL1 and PL2 privilege levels deller
2023-08-25 6:56 ` [PATCH v2 2/5] target/hppa: Add privilege to MMU index conversion helpers deller
2023-08-25 6:56 ` deller [this message]
2023-08-25 6:56 ` [PATCH v2 4/5] target/hppa: Use privilege helper in hppa_get_physical_address() deller
2023-08-25 6:56 ` [PATCH v2 5/5] target/hppa: Switch to use MMU indices 11-15 deller
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