From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: anton.kochkov@proton.me, kbastian@mail.uni-paderborn.de
Subject: [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT
Date: Sat, 26 Aug 2023 18:02:40 +0200 [thread overview]
Message-ID: <20230826160242.312052-9-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230826160242.312052-1-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8 ++++----
tests/tcg/tricore/asm/macros.h | 9 +++++++++
tests/tcg/tricore/asm/test_insert.S | 5 +++++
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d13f85c03a..a68660b326 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8225,12 +8225,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
- CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r2);
- tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+ tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
- gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+ gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
)
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(EREG_RS2_LO, rs2_lo); \
+ LI(EREG_RS2_HI, rs2_hi); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2; \
+ )
+
#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@ _start:
# | | | | | | |
TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+# insn num result rs1 imm1 rs2_h rs2_l
+# | | | | | | |
+ TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
+ TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
TEST_PASSFAIL
--
2.41.0
next prev parent reply other threads:[~2023-08-26 16:04 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 01/10] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-08-27 4:23 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 02/10] target/tricore: Implement CRCN insn Bastian Koppelmann
2023-08-27 4:33 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-08-27 4:37 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 04/10] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-08-27 4:50 ` Richard Henderson
2023-08-27 11:07 ` Bastian Koppelmann
2023-08-27 14:49 ` Richard Henderson
2023-08-27 16:36 ` Bastian Koppelmann
2023-08-27 18:32 ` Richard Henderson
2023-08-27 18:59 ` Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 05/10] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-08-27 4:55 ` Richard Henderson
2023-08-27 7:09 ` Bastian Koppelmann
2023-08-27 14:51 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 06/10] target/tricore: Implement hptof insn Bastian Koppelmann
2023-08-27 4:56 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
2023-08-27 4:59 ` Richard Henderson
2023-08-26 16:02 ` Bastian Koppelmann [this message]
2023-08-27 5:06 ` [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT Richard Henderson
2023-08-27 7:18 ` Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 09/10] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-08-27 5:06 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-08-27 5:06 ` Richard Henderson
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