[RFC PATCH v2 0/6] Add API for list cpu extensions

[RFC PATCH v2 0/6] Add API for list cpu extensions

[LIU Zhiwei]

Some times we want to know what is the really mean of one cpu option.
For example, in RISC-V, we usually specify a cpu in this way:
-cpu rv64,v=on

If we don't look into the source code, we can't get the ISA extensions
of this -cpu command line.

In this patch set, we add one list_cpu_props API for common cores. It
will output the enabled ISA extensions.

In the near future, I will also list all possible user configurable
options and all possible extensions for this cpu.

In order to reuse the options parse code, I also add a QemuOptsList
for cpu.

After this patch, we can output the extensions for cpu,
"""
./qemu-system-riscv64 -cpu rv64,help
Enabled extensions:
    rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
To get all configuable options for this cpu, use -device rv64-riscv-cpu,help
"""


v1->v2:

1) Give a hint to use -device cpu,help for configualbe options on cpu
2) Support list_cpu_props for linux user mode
3) Add default to some properties to make -device cpu,help output better


Todo:
1) Fix Daniel comments on KVM and cpu option check
2) Add support for other archs
3) Move qdev help function from qdev-monitor to qdev-property

LIU Zhiwei (6):
  cpu: Add new API cpu_type_by_name
  target/riscv: Add API list_cpu_props
  softmmu/vl: Add qemu_cpu_opts QemuOptsList
  target/riscv: Add default value for misa property
  target/riscv: Add defalut value for string property
  linux-user: Move qemu_cpu_opts to cpu.c

 cpu.c                        | 63 +++++++++++++++++++++++++++++-------
 hw/core/qdev-prop-internal.h |  2 ++
 hw/core/qdev-properties.c    |  7 ++++
 include/exec/cpu-common.h    |  3 ++
 include/hw/core/cpu.h        | 11 +++++++
 include/hw/qdev-properties.h |  8 +++++
 linux-user/main.c            | 10 ++++++
 softmmu/vl.c                 | 11 +++++++
 target/riscv/cpu.c           | 30 +++++++++++++----
 target/riscv/cpu.h           |  2 ++
 10 files changed, 128 insertions(+), 19 deletions(-)

-- 
2.17.1

[RFC PATCH v2 1/6] cpu: Add new API cpu_type_by_name

[LIU Zhiwei]

cpu_type_by_name is used to get the cpu type name from the command
line -cpu.

Currently it is only used by parse_cpu_option. In the next patch, it
will be used by other cpu query functions.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 cpu.c | 31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/cpu.c b/cpu.c
index 1c948d1161..e1a9239d0f 100644
--- a/cpu.c
+++ b/cpu.c
@@ -257,28 +257,35 @@ void cpu_exec_initfn(CPUState *cpu)
 #endif
 }
 
-const char *parse_cpu_option(const char *cpu_option)
+static const char *cpu_type_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
-    CPUClass *cc;
-    gchar **model_pieces;
     const char *cpu_type;
 
-    model_pieces = g_strsplit(cpu_option, ",", 2);
-    if (!model_pieces[0]) {
-        error_report("-cpu option cannot be empty");
-        exit(1);
-    }
 
-    oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
+    oc = cpu_class_by_name(CPU_RESOLVING_TYPE, cpu_model);
     if (oc == NULL) {
-        error_report("unable to find CPU model '%s'", model_pieces[0]);
-        g_strfreev(model_pieces);
+        error_report("unable to find CPU model '%s'", cpu_model);
         exit(EXIT_FAILURE);
     }
 
     cpu_type = object_class_get_name(oc);
-    cc = CPU_CLASS(oc);
+    return cpu_type;
+}
+
+const char *parse_cpu_option(const char *cpu_option)
+{
+    const char *cpu_type;
+    CPUClass *cc;
+    gchar **model_pieces;
+
+    model_pieces = g_strsplit(cpu_option, ",", 2);
+    if (!model_pieces[0]) {
+        error_report("-cpu option cannot be empty");
+        exit(1);
+    }
+    cpu_type = cpu_type_by_name(model_pieces[0]);
+    cc = CPU_CLASS(object_class_by_name(cpu_type));
     cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
     g_strfreev(model_pieces);
     return cpu_type;
-- 
2.17.1

[RFC PATCH v2 2/6] target/riscv: Add API list_cpu_props

[LIU Zhiwei]

This API used for output current configuration for one specified CPU.
Currently only RISC-V frontend implements this API.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 cpu.c                     |  8 ++++++++
 include/exec/cpu-common.h |  1 +
 target/riscv/cpu.c        | 14 ++++++++++++++
 target/riscv/cpu.h        |  2 ++
 4 files changed, 25 insertions(+)

diff --git a/cpu.c b/cpu.c
index e1a9239d0f..03a313cd72 100644
--- a/cpu.c
+++ b/cpu.c
@@ -299,6 +299,14 @@ void list_cpus(void)
 #endif
 }
 
+void list_cpu_props(CPUState *cs)
+{
+    /* XXX: implement xxx_cpu_list_props for targets that still miss it */
+#if defined(cpu_list_props)
+    cpu_list_props(cs);
+#endif
+}
+
 #if defined(CONFIG_USER_ONLY)
 void tb_invalidate_phys_addr(hwaddr addr)
 {
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 87dc9a752c..b3160d9218 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 
 /* vl.c */
 void list_cpus(void);
+void list_cpu_props(CPUState *);
 
 #endif /* CPU_COMMON_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453..c2f102fae1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2226,6 +2226,20 @@ void riscv_cpu_list(void)
     g_slist_free(list);
 }
 
+void riscv_cpu_list_props(CPUState *cs)
+{
+    char *enabled_isa;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+    ObjectClass *oc = OBJECT_CLASS(mcc);
+
+    enabled_isa = riscv_isa_string(RISCV_CPU(cs));
+    qemu_printf("Enabled extensions:\n");
+    qemu_printf("\t%s\n", enabled_isa);
+    qemu_printf("To get all configuable options for this cpu, use"
+                " -device %s,help\n", object_class_get_name(oc));
+}
+
 #define DEFINE_CPU(type_name, initfn)      \
     {                                      \
         .name = type_name,                 \
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6ea22e0eea..af1d47605b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         bool probe, uintptr_t retaddr);
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(void);
+void riscv_cpu_list_props(CPUState *cs);
 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 
 #define cpu_list riscv_cpu_list
+#define cpu_list_props riscv_cpu_list_props
 #define cpu_mmu_index riscv_cpu_mmu_index
 
 #ifndef CONFIG_USER_ONLY
-- 
2.17.1

[RFC PATCH v2 3/6] softmmu/vl: Add qemu_cpu_opts QemuOptsList

[LIU Zhiwei]

This make the cpu works the similar way like the -device option.

For device option,
"""
./qemu-system-riscv64 -device e1000,help
e1000 options:
  acpi-index=<uint32>    -  (default: 0)
  addr=<int32>           - Slot and optional function number, example: 06.0 or 06 (default: -1)
  autonegotiation=<bool> - on/off (default: true)
  bootindex=<int32>
  extra_mac_registers=<bool> - on/off (default: true)
  failover_pair_id=<str>
"""

After this patch, the cpu can output its configurations,
"""
./qemu-system-riscv64 -cpu rv64,help
Enable extension:
	rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
"""

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 cpu.c                 |  2 +-
 include/hw/core/cpu.h | 11 +++++++++++
 softmmu/vl.c          | 35 +++++++++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/cpu.c b/cpu.c
index 03a313cd72..712bd02684 100644
--- a/cpu.c
+++ b/cpu.c
@@ -257,7 +257,7 @@ void cpu_exec_initfn(CPUState *cpu)
 #endif
 }
 
-static const char *cpu_type_by_name(const char *cpu_model)
+const char *cpu_type_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
     const char *cpu_type;
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fdcbe87352..49d41afdfa 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -657,6 +657,17 @@ CPUState *cpu_create(const char *typename);
  */
 const char *parse_cpu_option(const char *cpu_option);
 
+/**
+ * cpu_type_by_name:
+ * @cpu_model: The -cpu command line model name.
+ *
+ * Looks up type name by the -cpu command line model name
+ *
+ * Returns: type name of CPU or prints error and terminates process
+ *          if an error occurred.
+ */
+const char *cpu_type_by_name(const char *cpu_model);
+
 /**
  * cpu_has_work:
  * @cpu: The vCPU to check.
diff --git a/softmmu/vl.c b/softmmu/vl.c
index b0b96f67fa..bc30f3954d 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -218,6 +218,15 @@ static struct {
     { .driver = "virtio-vga-gl",        .flag = &default_vga       },
 };
 
+static QemuOptsList qemu_cpu_opts = {
+    .name = "cpu",
+    .implied_opt_name = "cpu_model",
+    .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
+    .desc = {
+        { /* end of list */ }
+    },
+};
+
 static QemuOptsList qemu_rtc_opts = {
     .name = "rtc",
     .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head),
@@ -1140,6 +1149,21 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp)
     return 0;
 }
 
+static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
+{
+    const char *cpu_model, *cpu_type;
+    cpu_model = qemu_opt_get(opts, "cpu_model");
+    if (!cpu_model) {
+        return 1;
+    }
+    if (!qemu_opt_has_help_opt(opts)) {
+        return 0;
+    }
+    cpu_type = cpu_type_by_name(cpu_model);
+    list_cpu_props((CPUState *)object_new(cpu_type));
+    return 1;
+}
+
 static int device_help_func(void *opaque, QemuOpts *opts, Error **errp)
 {
     return qdev_device_help(opts);
@@ -2467,6 +2491,11 @@ static void qemu_process_help_options(void)
         exit(0);
     }
 
+    if (qemu_opts_foreach(qemu_find_opts("cpu"),
+                          cpu_help_func, NULL, NULL)) {
+        exit(0);
+    }
+
     if (qemu_opts_foreach(qemu_find_opts("device"),
                           device_help_func, NULL, NULL)) {
         exit(0);
@@ -2680,6 +2709,7 @@ void qemu_init(int argc, char **argv)
     qemu_add_drive_opts(&bdrv_runtime_opts);
     qemu_add_opts(&qemu_chardev_opts);
     qemu_add_opts(&qemu_device_opts);
+    qemu_add_opts(&qemu_cpu_opts);
     qemu_add_opts(&qemu_netdev_opts);
     qemu_add_opts(&qemu_nic_opts);
     qemu_add_opts(&qemu_net_opts);
@@ -2756,6 +2786,11 @@ void qemu_init(int argc, char **argv)
             case QEMU_OPTION_cpu:
                 /* hw initialization will check this */
                 cpu_option = optarg;
+                opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"),
+                                               optarg, true);
+                if (!opts) {
+                    exit(1);
+                }
                 break;
             case QEMU_OPTION_hda:
             case QEMU_OPTION_hdb:
-- 
2.17.1

[RFC PATCH v2 4/6] target/riscv: Add default value for misa property

[LIU Zhiwei]

Before this patch,
"
qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help

...
v=<bool>               - Vector operations
...

"

After this patch,
"
v=<bool>               - Vector operations (default: false)
"

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 target/riscv/cpu.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c2f102fae1..38838cd2c0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1728,6 +1728,7 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     int i;
 
     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+        ObjectProperty *op;
         RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
         int bit = misa_cfg->misa_bit;
 
@@ -1739,14 +1740,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
             continue;
         }
 
-        object_property_add(cpu_obj, misa_cfg->name, "bool",
-                            cpu_get_misa_ext_cfg,
-                            cpu_set_misa_ext_cfg,
-                            NULL, (void *)misa_cfg);
+        op = object_property_add(cpu_obj, misa_cfg->name, "bool",
+                                 cpu_get_misa_ext_cfg,
+                                 cpu_set_misa_ext_cfg,
+                                 NULL, (void *)misa_cfg);
         object_property_set_description(cpu_obj, misa_cfg->name,
                                         misa_cfg->description);
-        object_property_set_bool(cpu_obj, misa_cfg->name,
-                                 misa_cfg->enabled, NULL);
+        object_property_set_default_bool(op, misa_cfg->enabled);
     }
 }
 
-- 
2.17.1

[RFC PATCH v2 5/6] target/riscv: Add defalut value for string property

[LIU Zhiwei]

Before this patch,
"""
qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help

...
vext_spec=<str>
...

"""

After this patch,
"""
vext_spec=<str>        -  (default: "v1.0")
"""

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 hw/core/qdev-prop-internal.h | 2 ++
 hw/core/qdev-properties.c    | 7 +++++++
 include/hw/qdev-properties.h | 8 ++++++++
 target/riscv/cpu.c           | 2 +-
 4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/hw/core/qdev-prop-internal.h b/hw/core/qdev-prop-internal.h
index d7b77844fe..f0613b9757 100644
--- a/hw/core/qdev-prop-internal.h
+++ b/hw/core/qdev-prop-internal.h
@@ -13,6 +13,8 @@ void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name,
 void qdev_propinfo_set_enum(Object *obj, Visitor *v, const char *name,
                             void *opaque, Error **errp);
 
+void qdev_propinfo_set_default_value_string(ObjectProperty *op,
+                                            const Property *prop);
 void qdev_propinfo_set_default_value_enum(ObjectProperty *op,
                                           const Property *prop);
 void qdev_propinfo_set_default_value_int(ObjectProperty *op,
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index 357b8761b5..64f70a7292 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -96,6 +96,12 @@ static ObjectPropertyAccessor *field_prop_setter(const PropertyInfo *info)
     return info->set ? field_prop_set : NULL;
 }
 
+void qdev_propinfo_set_default_value_string(ObjectProperty *op,
+                                            const Property *prop)
+{
+    object_property_set_default_str(op, prop->defval.p);
+}
+
 void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name,
                             void *opaque, Error **errp)
 {
@@ -488,6 +494,7 @@ const PropertyInfo qdev_prop_string = {
     .release = release_string,
     .get   = get_string,
     .set   = set_string,
+    .set_default_value = qdev_propinfo_set_default_value_string,
 };
 
 /* --- on/off/auto --- */
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index e1df08876c..8e5651724a 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -22,6 +22,7 @@ struct Property {
     union {
         int64_t i;
         uint64_t u;
+        void *p;
     } defval;
     int          arrayoffset;
     const PropertyInfo *arrayinfo;
@@ -91,6 +92,11 @@ extern const PropertyInfo qdev_prop_link;
                 .set_default = true,                                       \
                 .defval.u  = (_type)_defval)
 
+#define DEFINE_PROP_STR(_name, _state, _field, _defval, _prop, _type)      \
+    DEFINE_PROP(_name, _state, _field, _prop, _type,                       \
+                .set_default = true,                                       \
+                .defval.p  = (_type)_defval)
+
 #define DEFINE_PROP_UNSIGNED_NODEFAULT(_name, _state, _field, _prop, _type) \
     DEFINE_PROP(_name, _state, _field, _prop, _type)
 
@@ -171,6 +177,8 @@ extern const PropertyInfo qdev_prop_link;
     DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_size, uint64_t)
 #define DEFINE_PROP_STRING(_n, _s, _f)             \
     DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*)
+#define DEFINE_PROP_STRING_DEF(_n, _s, _f, _d)             \
+    DEFINE_PROP_STR(_n, _s, _f, _d, qdev_prop_string, char*)
 #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
 #define DEFINE_PROP_SIZE32(_n, _s, _f, _d)                       \
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 38838cd2c0..edcd34e62b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1769,7 +1769,7 @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
 
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+    DEFINE_PROP_STRING_DEF("vext_spec", RISCVCPU, cfg.vext_spec, "v1.0"),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
-- 
2.17.1

[RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c

[LIU Zhiwei]

Make qemu_cpu_opts also works for linux user mode. Notice, currently
qdev monitor is not included in linux user mode. We just output
current enabled extentions for RISC-V(without the hint to print all
properties with -device).

With this patch,
"""
qemu-riscv64 -cpu rv64,help
Enabled extensions:
	rv64_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
"""

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 cpu.c                     | 24 ++++++++++++++++++++++++
 include/exec/cpu-common.h |  2 ++
 linux-user/main.c         | 10 ++++++++++
 softmmu/vl.c              | 24 ------------------------
 target/riscv/cpu.c        |  8 +++++---
 5 files changed, 41 insertions(+), 27 deletions(-)

diff --git a/cpu.c b/cpu.c
index 712bd02684..590d75def0 100644
--- a/cpu.c
+++ b/cpu.c
@@ -47,6 +47,30 @@
 uintptr_t qemu_host_page_size;
 intptr_t qemu_host_page_mask;
 
+QemuOptsList qemu_cpu_opts = {
+    .name = "cpu",
+    .implied_opt_name = "cpu_model",
+    .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
+    .desc = {
+        { /* end of list */ }
+    },
+};
+
+int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
+{
+    const char *cpu_model, *cpu_type;
+    cpu_model = qemu_opt_get(opts, "cpu_model");
+    if (!cpu_model) {
+        return 1;
+    }
+    if (!qemu_opt_has_help_opt(opts)) {
+        return 0;
+    }
+    cpu_type = cpu_type_by_name(cpu_model);
+    list_cpu_props((CPUState *)object_new(cpu_type));
+    return 1;
+}
+
 #ifndef CONFIG_USER_ONLY
 static int cpu_common_post_load(void *opaque, int version_id)
 {
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b3160d9218..4d385436a5 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -168,4 +168,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 void list_cpus(void);
 void list_cpu_props(CPUState *);
 
+int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp);
+extern QemuOptsList qemu_cpu_opts;
 #endif /* CPU_COMMON_H */
diff --git a/linux-user/main.c b/linux-user/main.c
index 96be354897..c3ef84b1a7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -362,6 +362,15 @@ static void handle_arg_cpu(const char *arg)
         list_cpus();
         exit(EXIT_FAILURE);
     }
+    QemuOpts *opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"),
+                                             arg, true);
+    if (!opts) {
+        exit(1);
+    }
+    if (qemu_opts_foreach(qemu_find_opts("cpu"),
+                          cpu_help_func, NULL, NULL)) {
+        exit(0);
+    }
 }
 
 static void handle_arg_guest_base(const char *arg)
@@ -720,6 +729,7 @@ int main(int argc, char **argv, char **envp)
     cpu_model = NULL;
 
     qemu_add_opts(&qemu_trace_opts);
+    qemu_add_opts(&qemu_cpu_opts);
     qemu_plugin_add_opts();
 
     optind = parse_args(argc, argv);
diff --git a/softmmu/vl.c b/softmmu/vl.c
index bc30f3954d..d6a395454a 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -218,15 +218,6 @@ static struct {
     { .driver = "virtio-vga-gl",        .flag = &default_vga       },
 };
 
-static QemuOptsList qemu_cpu_opts = {
-    .name = "cpu",
-    .implied_opt_name = "cpu_model",
-    .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
-    .desc = {
-        { /* end of list */ }
-    },
-};
-
 static QemuOptsList qemu_rtc_opts = {
     .name = "rtc",
     .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head),
@@ -1149,21 +1140,6 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp)
     return 0;
 }
 
-static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
-{
-    const char *cpu_model, *cpu_type;
-    cpu_model = qemu_opt_get(opts, "cpu_model");
-    if (!cpu_model) {
-        return 1;
-    }
-    if (!qemu_opt_has_help_opt(opts)) {
-        return 0;
-    }
-    cpu_type = cpu_type_by_name(cpu_model);
-    list_cpu_props((CPUState *)object_new(cpu_type));
-    return 1;
-}
-
 static int device_help_func(void *opaque, QemuOpts *opts, Error **errp)
 {
     return qdev_device_help(opts);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index edcd34e62b..e4318fcc46 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2229,15 +2229,17 @@ void riscv_cpu_list(void)
 void riscv_cpu_list_props(CPUState *cs)
 {
     char *enabled_isa;
-    RISCVCPU *cpu = RISCV_CPU(cs);
-    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-    ObjectClass *oc = OBJECT_CLASS(mcc);
 
     enabled_isa = riscv_isa_string(RISCV_CPU(cs));
     qemu_printf("Enabled extensions:\n");
     qemu_printf("\t%s\n", enabled_isa);
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+    ObjectClass *oc = OBJECT_CLASS(mcc);
     qemu_printf("To get all configuable options for this cpu, use"
                 " -device %s,help\n", object_class_get_name(oc));
+#endif
 }
 
 #define DEFINE_CPU(type_name, initfn)      \
-- 
2.17.1

Re: [RFC PATCH v2 4/6] target/riscv: Add default value for misa property

[Daniel Henrique Barboza]

On 8/28/23 05:45, LIU Zhiwei wrote:
> Before this patch,
> "
> qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help
> 
> ...
> v=<bool>               - Vector operations
> ...
> 
> "
> 
> After this patch,
> "
> v=<bool>               - Vector operations (default: false)
> "
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c2f102fae1..38838cd2c0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1728,6 +1728,7 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
>       int i;
>   
>       for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> +        ObjectProperty *op;
>           RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
>           int bit = misa_cfg->misa_bit;
>   
> @@ -1739,14 +1740,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
>               continue;
>           }
>   
> -        object_property_add(cpu_obj, misa_cfg->name, "bool",
> -                            cpu_get_misa_ext_cfg,
> -                            cpu_set_misa_ext_cfg,
> -                            NULL, (void *)misa_cfg);
> +        op = object_property_add(cpu_obj, misa_cfg->name, "bool",
> +                                 cpu_get_misa_ext_cfg,
> +                                 cpu_set_misa_ext_cfg,
> +                                 NULL, (void *)misa_cfg);
>           object_property_set_description(cpu_obj, misa_cfg->name,
>                                           misa_cfg->description);
> -        object_property_set_bool(cpu_obj, misa_cfg->name,
> -                                 misa_cfg->enabled, NULL);
> +        object_property_set_default_bool(op, misa_cfg->enabled);
>       }
>   }
>   

Re: [RFC PATCH v2 5/6] target/riscv: Add defalut value for string property

[Daniel Henrique Barboza]

On 8/28/23 05:45, LIU Zhiwei wrote:
> Before this patch,
> """
> qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help
> 
> ...
> vext_spec=<str>
> ...
> 
> """
> 
> After this patch,
> """
> vext_spec=<str>        -  (default: "v1.0")
> """
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---

Code LGTM.

Assuming that we'll need a new API to set default strings in hw/core/qdev-properties.c
(seems likely but we'll need more opinions on that) we'll need to split this patch in
two:

- one patch to add the new qdev_propinfo_set_default_value_string() into
hw/core/qdev-properties.c

- one to change target/riscv to use the newly created API


Thanks,


Daniel



>   hw/core/qdev-prop-internal.h | 2 ++
>   hw/core/qdev-properties.c    | 7 +++++++
>   include/hw/qdev-properties.h | 8 ++++++++
>   target/riscv/cpu.c           | 2 +-
>   4 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/core/qdev-prop-internal.h b/hw/core/qdev-prop-internal.h
> index d7b77844fe..f0613b9757 100644
> --- a/hw/core/qdev-prop-internal.h
> +++ b/hw/core/qdev-prop-internal.h
> @@ -13,6 +13,8 @@ void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name,
>   void qdev_propinfo_set_enum(Object *obj, Visitor *v, const char *name,
>                               void *opaque, Error **errp);
>   
> +void qdev_propinfo_set_default_value_string(ObjectProperty *op,
> +                                            const Property *prop);
>   void qdev_propinfo_set_default_value_enum(ObjectProperty *op,
>                                             const Property *prop);
>   void qdev_propinfo_set_default_value_int(ObjectProperty *op,
> diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
> index 357b8761b5..64f70a7292 100644
> --- a/hw/core/qdev-properties.c
> +++ b/hw/core/qdev-properties.c
> @@ -96,6 +96,12 @@ static ObjectPropertyAccessor *field_prop_setter(const PropertyInfo *info)
>       return info->set ? field_prop_set : NULL;
>   }
>   
> +void qdev_propinfo_set_default_value_string(ObjectProperty *op,
> +                                            const Property *prop)
> +{
> +    object_property_set_default_str(op, prop->defval.p);
> +}
> +
>   void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name,
>                               void *opaque, Error **errp)
>   {
> @@ -488,6 +494,7 @@ const PropertyInfo qdev_prop_string = {
>       .release = release_string,
>       .get   = get_string,
>       .set   = set_string,
> +    .set_default_value = qdev_propinfo_set_default_value_string,
>   };
>   
>   /* --- on/off/auto --- */
> diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
> index e1df08876c..8e5651724a 100644
> --- a/include/hw/qdev-properties.h
> +++ b/include/hw/qdev-properties.h
> @@ -22,6 +22,7 @@ struct Property {
>       union {
>           int64_t i;
>           uint64_t u;
> +        void *p;
>       } defval;
>       int          arrayoffset;
>       const PropertyInfo *arrayinfo;
> @@ -91,6 +92,11 @@ extern const PropertyInfo qdev_prop_link;
>                   .set_default = true,                                       \
>                   .defval.u  = (_type)_defval)
>   
> +#define DEFINE_PROP_STR(_name, _state, _field, _defval, _prop, _type)      \
> +    DEFINE_PROP(_name, _state, _field, _prop, _type,                       \
> +                .set_default = true,                                       \
> +                .defval.p  = (_type)_defval)
> +
>   #define DEFINE_PROP_UNSIGNED_NODEFAULT(_name, _state, _field, _prop, _type) \
>       DEFINE_PROP(_name, _state, _field, _prop, _type)
>   
> @@ -171,6 +177,8 @@ extern const PropertyInfo qdev_prop_link;
>       DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_size, uint64_t)
>   #define DEFINE_PROP_STRING(_n, _s, _f)             \
>       DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*)
> +#define DEFINE_PROP_STRING_DEF(_n, _s, _f, _d)             \
> +    DEFINE_PROP_STR(_n, _s, _f, _d, qdev_prop_string, char*)
>   #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
>       DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
>   #define DEFINE_PROP_SIZE32(_n, _s, _f, _d)                       \
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 38838cd2c0..edcd34e62b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1769,7 +1769,7 @@ static Property riscv_cpu_extensions[] = {
>       DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
>   
>       DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> -    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> +    DEFINE_PROP_STRING_DEF("vext_spec", RISCVCPU, cfg.vext_spec, "v1.0"),
>       DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
>       DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>   

Re: [RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c

[Daniel Henrique Barboza]

On 8/28/23 05:45, LIU Zhiwei wrote:
> Make qemu_cpu_opts also works for linux user mode. Notice, currently
> qdev monitor is not included in linux user mode. We just output
> current enabled extentions for RISC-V(without the hint to print all
> properties with -device).
> 
> With this patch,
> """
> qemu-riscv64 -cpu rv64,help
> Enabled extensions:
> 	rv64_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
> """
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---


This is a similar to patch 5. Code LGTM but it's better to split the changes made in
the common code from the changes in a specific target.

What I suggest here is add a patch with the linux-user changes alone, then a second
patch with the target/riscv changes. Thanks,


Daniel


>   cpu.c                     | 24 ++++++++++++++++++++++++
>   include/exec/cpu-common.h |  2 ++
>   linux-user/main.c         | 10 ++++++++++
>   softmmu/vl.c              | 24 ------------------------
>   target/riscv/cpu.c        |  8 +++++---
>   5 files changed, 41 insertions(+), 27 deletions(-)
> 
> diff --git a/cpu.c b/cpu.c
> index 712bd02684..590d75def0 100644
> --- a/cpu.c
> +++ b/cpu.c
> @@ -47,6 +47,30 @@
>   uintptr_t qemu_host_page_size;
>   intptr_t qemu_host_page_mask;
>   
> +QemuOptsList qemu_cpu_opts = {
> +    .name = "cpu",
> +    .implied_opt_name = "cpu_model",
> +    .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
> +    .desc = {
> +        { /* end of list */ }
> +    },
> +};
> +
> +int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
> +{
> +    const char *cpu_model, *cpu_type;
> +    cpu_model = qemu_opt_get(opts, "cpu_model");
> +    if (!cpu_model) {
> +        return 1;
> +    }
> +    if (!qemu_opt_has_help_opt(opts)) {
> +        return 0;
> +    }
> +    cpu_type = cpu_type_by_name(cpu_model);
> +    list_cpu_props((CPUState *)object_new(cpu_type));
> +    return 1;
> +}
> +
>   #ifndef CONFIG_USER_ONLY
>   static int cpu_common_post_load(void *opaque, int version_id)
>   {
> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
> index b3160d9218..4d385436a5 100644
> --- a/include/exec/cpu-common.h
> +++ b/include/exec/cpu-common.h
> @@ -168,4 +168,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
>   void list_cpus(void);
>   void list_cpu_props(CPUState *);
>   
> +int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp);
> +extern QemuOptsList qemu_cpu_opts;
>   #endif /* CPU_COMMON_H */
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 96be354897..c3ef84b1a7 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -362,6 +362,15 @@ static void handle_arg_cpu(const char *arg)
>           list_cpus();
>           exit(EXIT_FAILURE);
>       }
> +    QemuOpts *opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"),
> +                                             arg, true);
> +    if (!opts) {
> +        exit(1);
> +    }
> +    if (qemu_opts_foreach(qemu_find_opts("cpu"),
> +                          cpu_help_func, NULL, NULL)) {
> +        exit(0);
> +    }
>   }
>   
>   static void handle_arg_guest_base(const char *arg)
> @@ -720,6 +729,7 @@ int main(int argc, char **argv, char **envp)
>       cpu_model = NULL;
>   
>       qemu_add_opts(&qemu_trace_opts);
> +    qemu_add_opts(&qemu_cpu_opts);
>       qemu_plugin_add_opts();
>   
>       optind = parse_args(argc, argv);
> diff --git a/softmmu/vl.c b/softmmu/vl.c
> index bc30f3954d..d6a395454a 100644
> --- a/softmmu/vl.c
> +++ b/softmmu/vl.c
> @@ -218,15 +218,6 @@ static struct {
>       { .driver = "virtio-vga-gl",        .flag = &default_vga       },
>   };
>   
> -static QemuOptsList qemu_cpu_opts = {
> -    .name = "cpu",
> -    .implied_opt_name = "cpu_model",
> -    .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
> -    .desc = {
> -        { /* end of list */ }
> -    },
> -};
> -
>   static QemuOptsList qemu_rtc_opts = {
>       .name = "rtc",
>       .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head),
> @@ -1149,21 +1140,6 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp)
>       return 0;
>   }
>   
> -static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
> -{
> -    const char *cpu_model, *cpu_type;
> -    cpu_model = qemu_opt_get(opts, "cpu_model");
> -    if (!cpu_model) {
> -        return 1;
> -    }
> -    if (!qemu_opt_has_help_opt(opts)) {
> -        return 0;
> -    }
> -    cpu_type = cpu_type_by_name(cpu_model);
> -    list_cpu_props((CPUState *)object_new(cpu_type));
> -    return 1;
> -}
> -
>   static int device_help_func(void *opaque, QemuOpts *opts, Error **errp)
>   {
>       return qdev_device_help(opts);
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index edcd34e62b..e4318fcc46 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2229,15 +2229,17 @@ void riscv_cpu_list(void)
>   void riscv_cpu_list_props(CPUState *cs)
>   {
>       char *enabled_isa;
> -    RISCVCPU *cpu = RISCV_CPU(cs);
> -    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> -    ObjectClass *oc = OBJECT_CLASS(mcc);
>   
>       enabled_isa = riscv_isa_string(RISCV_CPU(cs));
>       qemu_printf("Enabled extensions:\n");
>       qemu_printf("\t%s\n", enabled_isa);
> +#ifndef CONFIG_USER_ONLY
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> +    ObjectClass *oc = OBJECT_CLASS(mcc);
>       qemu_printf("To get all configuable options for this cpu, use"
>                   " -device %s,help\n", object_class_get_name(oc));
> +#endif
>   }
>   
>   #define DEFINE_CPU(type_name, initfn)      \

Re: [RFC PATCH v2 0/6] Add API for list cpu extensions

[Igor Mammedov]

On Mon, 28 Aug 2023 16:45:30 +0800
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:

> Some times we want to know what is the really mean of one cpu option.
> For example, in RISC-V, we usually specify a cpu in this way:
> -cpu rv64,v=on
> 
> If we don't look into the source code, we can't get the ISA extensions
> of this -cpu command line.
> 
> In this patch set, we add one list_cpu_props API for common cores. It
> will output the enabled ISA extensions.
> 
> In the near future, I will also list all possible user configurable
> options and all possible extensions for this cpu.
> 
> In order to reuse the options parse code, I also add a QemuOptsList
> for cpu.
> 
> After this patch, we can output the extensions for cpu,
> """
> ./qemu-system-riscv64 -cpu rv64,help
> Enabled extensions:
>     rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu

It's not that easy to get features with values in general.
(many factors influence defaults, which may include:
 * properties set and/or added at realize time
 * defaults amended by machine type version
 * defaults amended by -global CLI options
)

To do that consensus was to query features after CPU object is realized.
Typically that implies starting dummy QEMU with needed CPU model and
then using query-cpu-model-expansion command to get actual property values.
 
The task is solved by implementing query-cpu-model-expansion
command so that user (mainly management layer) could get defaults via QMP.
So if your goal is to get the given cpu defaults to mgmt layer
it is sufficient to implement query-cpu-model-expansion command for riscv.
(CC-ing libvirt folks to see if it picks up the command
automatically for every target or some more work would be needed
on their side as well)

PS:
no one cared about making -cpu name,help working till this moment
and certainly not for linux-user part.

To make this option work reliably it's would be necessary to make sure
that query-cpu-model-expansion work in user mode as well.

Also the timing when 'help' is processed should ensure that
machine is available/initialized (i.e. compat properties are in effect) 

Once you have working query-cpu-model-expansion, your new -cpu foo,help handler
can translate json to human readable format that everyone would agree upon.

> To get all configuable options for this cpu, use -device rv64-riscv-cpu,help
> """
> 
> 
> v1->v2:
> 
> 1) Give a hint to use -device cpu,help for configualbe options on cpu
> 2) Support list_cpu_props for linux user mode
> 3) Add default to some properties to make -device cpu,help output better
> 
> 
> Todo:
> 1) Fix Daniel comments on KVM and cpu option check
> 2) Add support for other archs
> 3) Move qdev help function from qdev-monitor to qdev-property
> 
> LIU Zhiwei (6):
>   cpu: Add new API cpu_type_by_name
>   target/riscv: Add API list_cpu_props
>   softmmu/vl: Add qemu_cpu_opts QemuOptsList
>   target/riscv: Add default value for misa property
>   target/riscv: Add defalut value for string property
>   linux-user: Move qemu_cpu_opts to cpu.c
> 
>  cpu.c                        | 63 +++++++++++++++++++++++++++++-------
>  hw/core/qdev-prop-internal.h |  2 ++
>  hw/core/qdev-properties.c    |  7 ++++
>  include/exec/cpu-common.h    |  3 ++
>  include/hw/core/cpu.h        | 11 +++++++
>  include/hw/qdev-properties.h |  8 +++++
>  linux-user/main.c            | 10 ++++++
>  softmmu/vl.c                 | 11 +++++++
>  target/riscv/cpu.c           | 30 +++++++++++++----
>  target/riscv/cpu.h           |  2 ++
>  10 files changed, 128 insertions(+), 19 deletions(-)
> 

Re: [RFC PATCH v2 0/6] Add API for list cpu extensions

[Daniel Henrique Barboza]

On 8/28/23 10:58, Igor Mammedov wrote:
> On Mon, 28 Aug 2023 16:45:30 +0800
> LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
> 
>> Some times we want to know what is the really mean of one cpu option.
>> For example, in RISC-V, we usually specify a cpu in this way:
>> -cpu rv64,v=on
>>
>> If we don't look into the source code, we can't get the ISA extensions
>> of this -cpu command line.
>>
>> In this patch set, we add one list_cpu_props API for common cores. It
>> will output the enabled ISA extensions.
>>
>> In the near future, I will also list all possible user configurable
>> options and all possible extensions for this cpu.
>>
>> In order to reuse the options parse code, I also add a QemuOptsList
>> for cpu.
>>
>> After this patch, we can output the extensions for cpu,
>> """
>> ./qemu-system-riscv64 -cpu rv64,help
>> Enabled extensions:
>>      rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
> 
> It's not that easy to get features with values in general.
> (many factors influence defaults, which may include:
>   * properties set and/or added at realize time
>   * defaults amended by machine type version
>   * defaults amended by -global CLI options
> )
> 
> To do that consensus was to query features after CPU object is realized.
> Typically that implies starting dummy QEMU with needed CPU model and
> then using query-cpu-model-expansion command to get actual property values.

FWIW I have a working prototype of the query-cpu-model-expansion for RISC-V.
I'll send it to the ML when I'm done smoothing the rough edges (hopefully
end of this week).


>   
> The task is solved by implementing query-cpu-model-expansion
> command so that user (mainly management layer) could get defaults via QMP.
> So if your goal is to get the given cpu defaults to mgmt layer
> it is sufficient to implement query-cpu-model-expansion command for riscv.
> (CC-ing libvirt folks to see if it picks up the command
> automatically for every target or some more work would be needed
> on their side as well)
> 
> PS:
> no one cared about making -cpu name,help working till this moment
> and certainly not for linux-user part.
> 
> To make this option work reliably it's would be necessary to make sure
> that query-cpu-model-expansion work in user mode as well.

I can take a look into how much extra code we need to support
query-cpu-model-expansion for user mode, but no promises. If it's too much
work I'd rather implement the API as is (like ARM and x86 already does) and
worry about supporting it for user-mode later.


Thanks,

Daniel


> 
> Also the timing when 'help' is processed should ensure that
> machine is available/initialized (i.e. compat properties are in effect)
> 
> Once you have working query-cpu-model-expansion, your new -cpu foo,help handler
> can translate json to human readable format that everyone would agree upon.
> 
>> To get all configuable options for this cpu, use -device rv64-riscv-cpu,help
>> """
>>
>>
>> v1->v2:
>>
>> 1) Give a hint to use -device cpu,help for configualbe options on cpu
>> 2) Support list_cpu_props for linux user mode
>> 3) Add default to some properties to make -device cpu,help output better
>>
>>
>> Todo:
>> 1) Fix Daniel comments on KVM and cpu option check
>> 2) Add support for other archs
>> 3) Move qdev help function from qdev-monitor to qdev-property
>>
>> LIU Zhiwei (6):
>>    cpu: Add new API cpu_type_by_name
>>    target/riscv: Add API list_cpu_props
>>    softmmu/vl: Add qemu_cpu_opts QemuOptsList
>>    target/riscv: Add default value for misa property
>>    target/riscv: Add defalut value for string property
>>    linux-user: Move qemu_cpu_opts to cpu.c
>>
>>   cpu.c                        | 63 +++++++++++++++++++++++++++++-------
>>   hw/core/qdev-prop-internal.h |  2 ++
>>   hw/core/qdev-properties.c    |  7 ++++
>>   include/exec/cpu-common.h    |  3 ++
>>   include/hw/core/cpu.h        | 11 +++++++
>>   include/hw/qdev-properties.h |  8 +++++
>>   linux-user/main.c            | 10 ++++++
>>   softmmu/vl.c                 | 11 +++++++
>>   target/riscv/cpu.c           | 30 +++++++++++++----
>>   target/riscv/cpu.h           |  2 ++
>>   10 files changed, 128 insertions(+), 19 deletions(-)
>>
> 

Re: [RFC PATCH v2 0/6] Add API for list cpu extensions

[LIU Zhiwei]

On 2023/8/28 21:58, Igor Mammedov wrote:
> On Mon, 28 Aug 2023 16:45:30 +0800
> LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
>> Some times we want to know what is the really mean of one cpu option.
>> For example, in RISC-V, we usually specify a cpu in this way:
>> -cpu rv64,v=on
>>
>> If we don't look into the source code, we can't get the ISA extensions
>> of this -cpu command line.
>>
>> In this patch set, we add one list_cpu_props API for common cores. It
>> will output the enabled ISA extensions.
>>
>> In the near future, I will also list all possible user configurable
>> options and all possible extensions for this cpu.
>>
>> In order to reuse the options parse code, I also add a QemuOptsList
>> for cpu.
>>
>> After this patch, we can output the extensions for cpu,
>> """
>> ./qemu-system-riscv64 -cpu rv64,help
>> Enabled extensions:
>>      rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
> It's not that easy to get features with values in general.
> (many factors influence defaults, which may include:
>   * properties set and/or added at realize time
>   * defaults amended by machine type version
>   * defaults amended by -global CLI options
> )
>
> To do that consensus was to query features after CPU object is realized.
> Typically that implies starting dummy QEMU with needed CPU model and
> then using query-cpu-model-expansion command to get actual property values.

I agree query-cpu-model-expansion command is necessary. But for users 
that manually

run qemu command line, it is difficult to for them to give a json-based 
input.

>   
> The task is solved by implementing query-cpu-model-expansion
> command so that user (mainly management layer) could get defaults via QMP.
> So if your goal is to get the given cpu defaults to mgmt layer
> it is sufficient to implement query-cpu-model-expansion command for riscv.
> (CC-ing libvirt folks to see if it picks up the command
> automatically for every target or some more work would be needed
> on their side as well)
>
> PS:
> no one cared about making -cpu name,help working till this moment
> and certainly not for linux-user part.
>
> To make this option work reliably it's would be necessary to make sure
> that query-cpu-model-expansion work in user mode as well.

>
> Also the timing when 'help' is processed should ensure that
> machine is available/initialized (i.e. compat properties are in effect)

Agree. I can defer the helper handler process to the machine initialized 
stage.

Thanks,
Zhiwei

>
> Once you have working query-cpu-model-expansion, your new -cpu foo,help handler
> can translate json to human readable format that everyone would agree upon.
>
>> To get all configuable options for this cpu, use -device rv64-riscv-cpu,help
>> """
>>
>>
>> v1->v2:
>>
>> 1) Give a hint to use -device cpu,help for configualbe options on cpu
>> 2) Support list_cpu_props for linux user mode
>> 3) Add default to some properties to make -device cpu,help output better
>>
>>
>> Todo:
>> 1) Fix Daniel comments on KVM and cpu option check
>> 2) Add support for other archs
>> 3) Move qdev help function from qdev-monitor to qdev-property
>>
>> LIU Zhiwei (6):
>>    cpu: Add new API cpu_type_by_name
>>    target/riscv: Add API list_cpu_props
>>    softmmu/vl: Add qemu_cpu_opts QemuOptsList
>>    target/riscv: Add default value for misa property
>>    target/riscv: Add defalut value for string property
>>    linux-user: Move qemu_cpu_opts to cpu.c
>>
>>   cpu.c                        | 63 +++++++++++++++++++++++++++++-------
>>   hw/core/qdev-prop-internal.h |  2 ++
>>   hw/core/qdev-properties.c    |  7 ++++
>>   include/exec/cpu-common.h    |  3 ++
>>   include/hw/core/cpu.h        | 11 +++++++
>>   include/hw/qdev-properties.h |  8 +++++
>>   linux-user/main.c            | 10 ++++++
>>   softmmu/vl.c                 | 11 +++++++
>>   target/riscv/cpu.c           | 30 +++++++++++++----
>>   target/riscv/cpu.h           |  2 ++
>>   10 files changed, 128 insertions(+), 19 deletions(-)
>>