From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com,
philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com,
berrange@redhat.com, richard.henderson@linaro.org,
laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, liweiwei@iscas.ac.cn,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
qemu-riscv@nongnu.org
Subject: [RFC PATCH v2 2/6] target/riscv: Add API list_cpu_props
Date: Mon, 28 Aug 2023 16:45:32 +0800 [thread overview]
Message-ID: <20230828084536.231-3-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com>
This API used for output current configuration for one specified CPU.
Currently only RISC-V frontend implements this API.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
cpu.c | 8 ++++++++
include/exec/cpu-common.h | 1 +
target/riscv/cpu.c | 14 ++++++++++++++
target/riscv/cpu.h | 2 ++
4 files changed, 25 insertions(+)
diff --git a/cpu.c b/cpu.c
index e1a9239d0f..03a313cd72 100644
--- a/cpu.c
+++ b/cpu.c
@@ -299,6 +299,14 @@ void list_cpus(void)
#endif
}
+void list_cpu_props(CPUState *cs)
+{
+ /* XXX: implement xxx_cpu_list_props for targets that still miss it */
+#if defined(cpu_list_props)
+ cpu_list_props(cs);
+#endif
+}
+
#if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(hwaddr addr)
{
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 87dc9a752c..b3160d9218 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
/* vl.c */
void list_cpus(void);
+void list_cpu_props(CPUState *);
#endif /* CPU_COMMON_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453..c2f102fae1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2226,6 +2226,20 @@ void riscv_cpu_list(void)
g_slist_free(list);
}
+void riscv_cpu_list_props(CPUState *cs)
+{
+ char *enabled_isa;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ ObjectClass *oc = OBJECT_CLASS(mcc);
+
+ enabled_isa = riscv_isa_string(RISCV_CPU(cs));
+ qemu_printf("Enabled extensions:\n");
+ qemu_printf("\t%s\n", enabled_isa);
+ qemu_printf("To get all configuable options for this cpu, use"
+ " -device %s,help\n", object_class_get_name(oc));
+}
+
#define DEFINE_CPU(type_name, initfn) \
{ \
.name = type_name, \
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6ea22e0eea..af1d47605b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
+void riscv_cpu_list_props(CPUState *cs);
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
#define cpu_list riscv_cpu_list
+#define cpu_list_props riscv_cpu_list_props
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
--
2.17.1
next prev parent reply other threads:[~2023-08-28 8:48 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-28 8:45 [RFC PATCH v2 0/6] Add API for list cpu extensions LIU Zhiwei
2023-08-28 8:45 ` [RFC PATCH v2 1/6] cpu: Add new API cpu_type_by_name LIU Zhiwei
2023-08-28 8:45 ` LIU Zhiwei [this message]
2023-08-28 8:45 ` [RFC PATCH v2 3/6] softmmu/vl: Add qemu_cpu_opts QemuOptsList LIU Zhiwei
2023-08-28 8:45 ` [RFC PATCH v2 4/6] target/riscv: Add default value for misa property LIU Zhiwei
2023-08-28 12:26 ` Daniel Henrique Barboza
2023-08-28 8:45 ` [RFC PATCH v2 5/6] target/riscv: Add defalut value for string property LIU Zhiwei
2023-08-28 12:31 ` Daniel Henrique Barboza
2023-08-28 8:45 ` [RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c LIU Zhiwei
2023-08-28 12:35 ` Daniel Henrique Barboza
2023-08-28 13:58 ` [RFC PATCH v2 0/6] Add API for list cpu extensions Igor Mammedov
2023-08-28 15:35 ` Daniel Henrique Barboza
2023-08-29 3:02 ` LIU Zhiwei
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