From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
Jiajie Chen <c@jia.je>, WANG Xuerui <git@xen0n.name>
Subject: [PATCH 07/11] tcg/loongarch64: Lower mul_vec to vmul
Date: Mon, 28 Aug 2023 23:19:45 +0800 [thread overview]
Message-ID: <20230828152009.352048-8-c@jia.je> (raw)
In-Reply-To: <20230828152009.352048-1-c@jia.je>
Signed-off-by: Jiajie Chen <c@jia.je>
---
tcg/loongarch64/tcg-target.c.inc | 8 ++++++++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 819dcdba77..bca24b6a20 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1641,6 +1641,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const LoongArchInsn neg_vec_insn[4] = {
OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D
};
+ static const LoongArchInsn mul_vec_insn[4] = {
+ OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D
+ };
a0 = args[0];
a1 = args[1];
@@ -1718,6 +1721,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_neg_vec:
tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1));
break;
+ case INDEX_op_mul_vec:
+ tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2));
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1743,6 +1749,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
case INDEX_op_nor_vec:
case INDEX_op_neg_vec:
+ case INDEX_op_mul_vec:
return 1;
default:
return 0;
@@ -1913,6 +1920,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
case INDEX_op_nor_vec:
+ case INDEX_op_mul_vec:
return C_O1_I2(w, w, w);
case INDEX_op_neg_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 6a8147875a..6b97abcb5b 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -182,7 +182,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_nand_vec 0
#define TCG_TARGET_HAS_nor_vec 1
#define TCG_TARGET_HAS_eqv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
--
2.42.0
next prev parent reply other threads:[~2023-08-28 15:22 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-28 15:19 [PATCH 00/11] Lower TCG vector ops to LSX Jiajie Chen
2023-08-28 15:19 ` [PATCH 01/11] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-08-28 15:19 ` [PATCH 02/11] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-08-28 16:57 ` Richard Henderson
2023-08-28 17:04 ` Jiajie Chen
2023-08-28 15:19 ` [PATCH 03/11] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-08-28 17:08 ` Richard Henderson
2023-08-28 15:19 ` [PATCH 04/11] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-08-28 17:13 ` Richard Henderson
2023-08-28 15:19 ` [PATCH 05/11] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-08-28 17:17 ` Richard Henderson
2023-08-28 15:19 ` [PATCH 06/11] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-08-28 17:18 ` Richard Henderson
2023-08-28 15:19 ` Jiajie Chen [this message]
2023-08-28 17:18 ` [PATCH 07/11] tcg/loongarch64: Lower mul_vec to vmul Richard Henderson
2023-08-28 15:19 ` [PATCH 08/11] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-08-28 17:19 ` Richard Henderson
2023-08-28 15:19 ` [PATCH 09/11] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-08-28 17:20 ` Richard Henderson
2023-08-28 15:19 ` [PATCH 10/11] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-08-28 17:21 ` Richard Henderson
2023-08-28 15:19 ` [PATCH 11/11] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-08-28 17:22 ` Richard Henderson
2023-08-28 17:29 ` [PATCH 00/11] Lower TCG vector ops to LSX Richard Henderson
2023-08-28 19:39 ` Richard Henderson
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