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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id dk24-20020a170906f0d800b00992d0de8762sm723518ejb.216.2023.08.31.05.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 05:49:01 -0700 (PDT) Date: Thu, 31 Aug 2023 14:49:00 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH RESEND v8 01/20] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Message-ID: <20230831-1bdbe4d2afbc10dd26f1892f@orel> References: <20230824221440.484675-1-dbarboza@ventanamicro.com> <20230824221440.484675-2-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230824221440.484675-2-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=ajones@ventanamicro.com; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 24, 2023 at 07:14:21PM -0300, Daniel Henrique Barboza wrote: > We'll add a new CPU type that will enable a considerable amount of > extensions. To make it easier for us we'll do a few cleanups in our > existing riscv_cpu_extensions[] array. > > Start by splitting all CPU non-boolean options from it. Create a new > riscv_cpu_options[] array for them. Add all these properties in > riscv_cpu_add_user_properties() as it is already being done today. > > 'mmu' and 'pmp' aren't really extensions in the usual way we think about > RISC-V extensions. These are closer to CPU features/options, so move > both to riscv_cpu_options[] too. In the near future we'll need to match > all extensions with all entries in isa_edata_arr[], and so it happens > that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv > spec version restriction). This further emphasizes the point that these > are more a CPU option than an extension. > > No functional changes made. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Weiwei Li > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 33 +++++++++++++++++++++++---------- > 1 file changed, 23 insertions(+), 10 deletions(-) > Reviewed-by: Andrew Jones