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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id g24-20020a170906395800b00992e265495csm687088eje.212.2023.08.31.05.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 05:06:05 -0700 (PDT) Date: Thu, 31 Aug 2023 14:06:04 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH 17/20] target/riscv/cpu.c: export isa_edata_arr[] Message-ID: <20230831-5326ae2dedf427e7ed8a4264@orel> References: <20230825130853.511782-1-dbarboza@ventanamicro.com> <20230825130853.511782-18-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230825130853.511782-18-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=ajones@ventanamicro.com; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 25, 2023 at 10:08:50AM -0300, Daniel Henrique Barboza wrote: > This array will be read by the TCG accel class, allowing it to handle > priv spec verifications on its own. The array will remain here in cpu.c > because it's also used by the riscv,isa string function. > > To export it we'll make it constant and finish it with an empty element ^ it's already constant > since ARRAY_SIZE() won't work outside of cpu.c. Get rid of its > ARRAY_SIZE() usage now to alleviate the changes for the next patch. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 47 +++++++++++++++++++++------------------------- > target/riscv/cpu.h | 7 +++++++ > 2 files changed, 28 insertions(+), 26 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3c9db46837..ac5ad4727c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, > RVC, RVS, RVU, RVH, RVJ, RVG}; > > -struct isa_ext_data { > - const char *name; > - int min_version; > - int ext_enable_offset; > -}; > - > -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ > - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} > - > /* > * From vector_helper.c > * Note that vector data is stored in host-endian 64-bit chunks, > @@ -61,6 +52,9 @@ struct isa_ext_data { > #define BYTE(x) (x) > #endif > > +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ > + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} > + > /* > * Here are the ordering rules of extension naming defined by RISC-V > * specification : > @@ -81,7 +75,7 @@ struct isa_ext_data { > * Single letter extensions are checked in riscv_cpu_validate_misa_priv() > * instead. > */ > -static const struct isa_ext_data isa_edata_arr[] = { > +const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), > ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), > ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), > @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), > ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), > ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), > + > + DEFINE_PROP_END_OF_LIST(), > }; > > bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) > @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) > > int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > { > - int i; > + const RISCVIsaExtData *edata; > > - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > - if (isa_edata_arr[i].ext_enable_offset != ext_offset) { > + for (edata = isa_edata_arr; edata && edata->name; edata++) { Just checking edata->name is sufficient. > + if (edata->ext_enable_offset != ext_offset) { > continue; > } > > - return isa_edata_arr[i].min_version; > + return edata->min_version; > } > > /* Default to oldest priv spec if no match found */ > @@ -933,22 +929,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > { > CPURISCVState *env = &cpu->env; > - int i; > + const RISCVIsaExtData *edata; > > /* Force disable extensions if priv spec version does not match */ > - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && > - (env->priv_ver < isa_edata_arr[i].min_version)) { > - isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, > - false); > + for (edata = isa_edata_arr; edata && edata->name; edata++) { > + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && > + (env->priv_ver < edata->min_version)) { > + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); > #ifndef CONFIG_USER_ONLY > warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > " because privilege spec version does not match", > - isa_edata_arr[i].name, env->mhartid); > + edata->name, env->mhartid); > #else > warn_report("disabling %s extension because " > "privilege spec version does not match", > - isa_edata_arr[i].name); > + edata->name); > #endif > } > } > @@ -1614,13 +1609,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, > int max_str_len) > { > + const RISCVIsaExtData *edata; > char *old = *isa_str; > char *new = *isa_str; > - int i; > > - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { > - new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); > + for (edata = isa_edata_arr; edata && edata->name; edata++) { > + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { > + new = g_strconcat(old, "_", edata->name, NULL); > g_free(old); > old = new; > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 4269523e24..d9a17df46a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > extern Property riscv_cpu_options[]; > > +typedef struct isa_ext_data { > + const char *name; > + int min_version; > + int ext_enable_offset; > +} RISCVIsaExtData; > +extern const RISCVIsaExtData isa_edata_arr[]; > + > void riscv_add_satp_mode_properties(Object *obj); > > /* CSR function table */ > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones