From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH 10/20] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
Date: Thu, 31 Aug 2023 13:22:21 +0200 [thread overview]
Message-ID: <20230831-838968c64dc3a2afa65e69bb@orel> (raw)
In-Reply-To: <20230825130853.511782-11-dbarboza@ventanamicro.com>
On Fri, Aug 25, 2023 at 10:08:43AM -0300, Daniel Henrique Barboza wrote:
> We'll introduce the KVM accelerator class with a 'cpu_instance_init'
> implementation that is going to be invoked during the common
> riscv_cpu_post_init() (via accel_cpu_instance_init()). This
> instance_init will execute KVM exclusive code that TCG doesn't care
> about, such as adding KVM specific properties, initing registers using a
> KVM scratch CPU and so on.
>
> The core of the forementioned cpu_instance_init impl is the current
> riscv_cpu_add_kvm_properties() that is being used by the common code via
> riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
> will all the relevant artifacts, exporting and renaming it to
> kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.
>
> To make this work we'll need to export riscv_cpu_extensions,
> riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
> well. The TCG accelerator will also need to access those in the near
> future so this export will benefit us in the long run.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 87 +++-------------------------------------
> target/riscv/cpu.h | 14 +++++++
> target/riscv/kvm.c | 66 +++++++++++++++++++++++++++++-
> target/riscv/kvm_riscv.h | 2 +-
> 4 files changed, 86 insertions(+), 83 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4eda853f1d..58b0ef2af8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1344,7 +1344,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> MISA_CFG(RVG, false),
> };
>
> -static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> +void riscv_cpu_add_misa_properties(Object *cpu_obj)
> {
> int i;
>
> @@ -1371,17 +1371,11 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> }
> }
>
> -typedef struct RISCVCPUMultiExtConfig {
> - const char *name;
> - uint32_t offset;
> - bool enabled;
> -} RISCVCPUMultiExtConfig;
> -
> #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
> .enabled = _defval}
>
> -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> /* Defaults for standard extensions */
> MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
> @@ -1441,7 +1435,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
> MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
> MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
> @@ -1459,7 +1453,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> };
>
> /* These are experimental so mark with 'x-' */
> -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> MULTI_EXT_CFG_BOOL("x-zicond", ext_zicond, false),
>
> /* ePMP 0.9.3 */
> @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static Property riscv_cpu_options[] = {
> +Property riscv_cpu_options[] = {
> DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> @@ -1548,25 +1542,6 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
> multi_cfg->enabled);
> }
>
> -#ifndef CONFIG_USER_ONLY
> -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
> - const char *name,
> - void *opaque, Error **errp)
> -{
> - const char *propname = opaque;
> - bool value;
> -
> - if (!visit_type_bool(v, name, &value, errp)) {
> - return;
> - }
> -
> - if (value) {
> - error_setg(errp, "extension %s is not available with KVM",
> - propname);
> - }
> -}
> -#endif
> -
> static void riscv_cpu_add_multiext_prop_array(Object *obj,
> const RISCVCPUMultiExtConfig *array)
> {
> @@ -1577,56 +1552,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
> }
> }
>
> -#ifndef CONFIG_USER_ONLY
> -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
> -{
> - /* Check if KVM created the property already */
> - if (object_property_find(obj, prop_name)) {
> - return;
> - }
> -
> - /*
> - * Set the default to disabled for every extension
> - * unknown to KVM and error out if the user attempts
> - * to enable any of them.
> - */
> - object_property_add(obj, prop_name, "bool",
> - NULL, cpu_set_cfg_unavailable,
> - NULL, (void *)prop_name);
> -}
> -
> -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
> - const RISCVCPUMultiExtConfig *array)
> -{
> - const RISCVCPUMultiExtConfig *prop;
> -
> - for (prop = array; prop && prop->name; prop++) {
> - riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
> - }
> -}
> -
> -static void riscv_cpu_add_kvm_properties(Object *obj)
> -{
> - Property *prop;
> - DeviceState *dev = DEVICE(obj);
> -
> - kvm_riscv_init_user_properties(obj);
> - riscv_cpu_add_misa_properties(obj);
> -
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
> -
> - for (prop = riscv_cpu_options; prop && prop->name; prop++) {
> - /* Check if KVM created the property already */
> - if (object_property_find(obj, prop->name)) {
> - continue;
> - }
> - qdev_property_add_static(dev, prop);
> - }
> -}
> -#endif
> -
> /*
> * Add CPU properties with user-facing flags.
> *
> @@ -1639,7 +1564,7 @@ static void riscv_cpu_add_user_properties(Object *obj)
> riscv_add_satp_mode_properties(obj);
>
> if (kvm_enabled()) {
> - riscv_cpu_add_kvm_properties(obj);
> + kvm_riscv_cpu_add_kvm_properties(obj);
> return;
> }
> #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 2ac00a0304..b9c4bea3f7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -22,6 +22,7 @@
>
> #include "hw/core/cpu.h"
> #include "hw/registerfields.h"
> +#include "hw/qdev-properties.h"
> #include "exec/cpu-defs.h"
> #include "qemu/cpu-float.h"
> #include "qom/object.h"
> @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
>
> +typedef struct RISCVCPUMultiExtConfig {
> + const char *name;
> + uint32_t offset;
> + bool enabled;
> +} RISCVCPUMultiExtConfig;
> +
> +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
> +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
> +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
> +extern Property riscv_cpu_options[];
> +
> +void riscv_cpu_add_misa_properties(Object *cpu_obj);
> +
> /* CSR function table */
> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 59004caa8e..7e67121456 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -338,6 +338,50 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
> }
> }
>
> +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
> + const char *name,
> + void *opaque, Error **errp)
> +{
> + const char *propname = opaque;
> + bool value;
> +
> + if (!visit_type_bool(v, name, &value, errp)) {
> + return;
> + }
> +
> + if (value) {
> + error_setg(errp, "extension %s is not available with KVM",
> + propname);
> + }
> +}
> +
> +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
> +{
> + /* Check if KVM created the property already */
> + if (object_property_find(obj, prop_name)) {
> + return;
> + }
> +
> + /*
> + * Set the default to disabled for every extension
> + * unknown to KVM and error out if the user attempts
> + * to enable any of them.
> + */
> + object_property_add(obj, prop_name, "bool",
> + NULL, cpu_set_cfg_unavailable,
> + NULL, (void *)prop_name);
> +}
> +
> +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
> + const RISCVCPUMultiExtConfig *array)
> +{
> + const RISCVCPUMultiExtConfig *prop;
> +
> + for (prop = array; prop && prop->name; prop++) {
> + riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
> + }
> +}
> +
> static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
> @@ -747,7 +791,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
> }
>
> -void kvm_riscv_init_user_properties(Object *cpu_obj)
> +static void riscv_init_user_properties(Object *cpu_obj)
> {
> RISCVCPU *cpu = RISCV_CPU(cpu_obj);
> KVMScratchCPU kvmcpu;
> @@ -1218,6 +1262,26 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
> }
>
> +void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> +{
> + DeviceState *dev = DEVICE(obj);
> +
> + riscv_init_user_properties(obj);
> + riscv_cpu_add_misa_properties(obj);
> +
> + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
> + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
> +
> + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> + /* Check if KVM created the property already */
> + if (object_property_find(obj, prop->name)) {
> + continue;
> + }
> + qdev_property_add_static(dev, prop);
> + }
> +}
> +
> static void riscv_host_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index 7d4b7c60e2..81e08b8359 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -19,7 +19,7 @@
> #ifndef QEMU_KVM_RISCV_H
> #define QEMU_KVM_RISCV_H
>
> -void kvm_riscv_init_user_properties(Object *cpu_obj);
> +void kvm_riscv_cpu_add_kvm_properties(Object *obj);
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> --
> 2.41.0
>
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-08-31 11:23 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 13:08 [PATCH 00/20] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 01/20] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-08-31 10:17 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 02/20] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-08-31 10:21 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 03/20] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-08-31 10:31 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 04/20] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
2023-08-28 16:30 ` Philippe Mathieu-Daudé
2023-08-31 10:38 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 05/20] target/riscv/cpu.c: add 'user_extension_properties' class prop Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 06/20] target/riscv: add 'max_features' CPU flag Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 07/20] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-08-31 11:00 ` Andrew Jones
2023-09-01 20:08 ` Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 08/20] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-08-28 16:35 ` Philippe Mathieu-Daudé
2023-08-31 11:04 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 09/20] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
2023-08-31 11:10 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 10/20] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-08-31 11:22 ` Andrew Jones [this message]
2023-08-25 13:08 ` [PATCH 11/20] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-08-28 16:38 ` Philippe Mathieu-Daudé
2023-08-29 13:16 ` Daniel Henrique Barboza
2023-08-31 11:26 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 12/20] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-08-28 16:47 ` Philippe Mathieu-Daudé
2023-08-30 18:21 ` Daniel Henrique Barboza
2023-08-30 20:54 ` Philippe Mathieu-Daudé
2023-08-31 11:30 ` Andrew Jones
2023-09-01 17:19 ` Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 13/20] target/riscv/kvm: refactor kvm_riscv_init_user_properties() Daniel Henrique Barboza
2023-08-31 11:34 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 14/20] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-08-31 11:50 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 15/20] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-08-31 11:56 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 16/20] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-08-31 12:01 ` Andrew Jones
2023-09-04 14:21 ` Daniel Henrique Barboza
2023-08-25 13:08 ` [PATCH 17/20] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-08-31 12:06 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 18/20] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
2023-08-31 12:07 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 19/20] target/riscv: add 'tcg_supported' class property Daniel Henrique Barboza
2023-08-31 12:25 ` Andrew Jones
2023-08-25 13:08 ` [PATCH 20/20] target/riscv: add 'kvm_supported' " Daniel Henrique Barboza
2023-08-31 12:47 ` Andrew Jones
2023-09-01 20:57 ` Daniel Henrique Barboza
2023-09-04 9:05 ` Andrew Jones
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