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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id f27-20020a170906391b00b0099cd1c0cb21sm668050eje.129.2023.08.31.05.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 05:01:27 -0700 (PDT) Date: Thu, 31 Aug 2023 14:01:26 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH 16/20] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Message-ID: <20230831-9135d7f6e2059b82be3f9300@orel> References: <20230825130853.511782-1-dbarboza@ventanamicro.com> <20230825130853.511782-17-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230825130853.511782-17-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=ajones@ventanamicro.com; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 25, 2023 at 10:08:49AM -0300, Daniel Henrique Barboza wrote: > All code related to MISA TCG properties is also moved. > > At this point, all TCG properties handling is done in tcg-cpu.c, all KVM > properties handling is done in kvm-cpu.c. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 89 -------------------------------------- > target/riscv/cpu.h | 1 - > target/riscv/tcg/tcg-cpu.c | 84 +++++++++++++++++++++++++++++++++++ > 3 files changed, 84 insertions(+), 90 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 89b09a7e89..3c9db46837 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1201,49 +1201,6 @@ static void riscv_cpu_init(Object *obj) > #endif /* CONFIG_USER_ONLY */ > } > > -typedef struct RISCVCPUMisaExtConfig { > - const char *name; > - const char *description; > - target_ulong misa_bit; > - bool enabled; > -} RISCVCPUMisaExtConfig; > - > -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > - void *opaque, Error **errp) > -{ > - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > - target_ulong misa_bit = misa_ext_cfg->misa_bit; > - RISCVCPU *cpu = RISCV_CPU(obj); > - CPURISCVState *env = &cpu->env; > - bool value; > - > - if (!visit_type_bool(v, name, &value, errp)) { > - return; > - } > - > - if (value) { > - env->misa_ext |= misa_bit; > - env->misa_ext_mask |= misa_bit; > - } else { > - env->misa_ext &= ~misa_bit; > - env->misa_ext_mask &= ~misa_bit; > - } > -} > - > -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > - void *opaque, Error **errp) > -{ > - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > - target_ulong misa_bit = misa_ext_cfg->misa_bit; > - RISCVCPU *cpu = RISCV_CPU(obj); > - CPURISCVState *env = &cpu->env; > - bool value; > - > - value = env->misa_ext & misa_bit; > - > - visit_type_bool(v, name, &value, errp); > -} > - > typedef struct misa_ext_info { > const char *name; > const char *description; > @@ -1304,52 +1261,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > return val; > } > > -#define MISA_CFG(_bit, _enabled) \ > - {.misa_bit = _bit, .enabled = _enabled} > - > -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > - MISA_CFG(RVA, true), > - MISA_CFG(RVC, true), > - MISA_CFG(RVD, true), > - MISA_CFG(RVF, true), > - MISA_CFG(RVI, true), > - MISA_CFG(RVE, false), > - MISA_CFG(RVM, true), > - MISA_CFG(RVS, true), > - MISA_CFG(RVU, true), > - MISA_CFG(RVH, true), > - MISA_CFG(RVJ, false), > - MISA_CFG(RVV, false), > - MISA_CFG(RVG, false), > -}; > - > -void riscv_cpu_add_misa_properties(Object *cpu_obj) > -{ > - int i; > - > - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { > - RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; > - int bit = misa_cfg->misa_bit; > - > - misa_cfg->name = riscv_get_misa_ext_name(bit); > - misa_cfg->description = riscv_get_misa_ext_description(bit); > - > - /* Check if KVM already created the property */ > - if (object_property_find(cpu_obj, misa_cfg->name)) { > - continue; > - } > - > - object_property_add(cpu_obj, misa_cfg->name, "bool", > - cpu_get_misa_ext_cfg, > - cpu_set_misa_ext_cfg, > - NULL, (void *)misa_cfg); > - object_property_set_description(cpu_obj, misa_cfg->name, > - misa_cfg->description); > - object_property_set_bool(cpu_obj, misa_cfg->name, > - misa_cfg->enabled, NULL); > - } > -} > - > #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ > {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ > .enabled = _defval} > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 74fbb33e09..4269523e24 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > extern Property riscv_cpu_options[]; > > -void riscv_cpu_add_misa_properties(Object *cpu_obj); > void riscv_add_satp_mode_properties(Object *obj); > > /* CSR function table */ > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 68ce3cbcb9..8e3f55d3a6 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -574,6 +574,90 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) > return true; > } > > +typedef struct RISCVCPUMisaExtConfig { > + const char *name; > + const char *description; > + target_ulong misa_bit; > + bool enabled; > +} RISCVCPUMisaExtConfig; > + > +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > + target_ulong misa_bit = misa_ext_cfg->misa_bit; > + RISCVCPU *cpu = RISCV_CPU(obj); > + CPURISCVState *env = &cpu->env; > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + if (value) { > + env->misa_ext |= misa_bit; > + env->misa_ext_mask |= misa_bit; > + } else { > + env->misa_ext &= ~misa_bit; > + env->misa_ext_mask &= ~misa_bit; > + } > +} > + > +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; > + target_ulong misa_bit = misa_ext_cfg->misa_bit; > + RISCVCPU *cpu = RISCV_CPU(obj); > + CPURISCVState *env = &cpu->env; > + bool value; > + > + value = env->misa_ext & misa_bit; > + > + visit_type_bool(v, name, &value, errp); > +} > + > +#define MISA_CFG(_bit, _enabled) \ > + {.misa_bit = _bit, .enabled = _enabled} > + > +static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { Can this be const? > + MISA_CFG(RVA, true), > + MISA_CFG(RVC, true), > + MISA_CFG(RVD, true), > + MISA_CFG(RVF, true), > + MISA_CFG(RVI, true), > + MISA_CFG(RVE, false), > + MISA_CFG(RVM, true), > + MISA_CFG(RVS, true), > + MISA_CFG(RVU, true), > + MISA_CFG(RVH, true), > + MISA_CFG(RVJ, false), > + MISA_CFG(RVV, false), > + MISA_CFG(RVG, false), > +}; > + > +static void riscv_cpu_add_misa_properties(Object *cpu_obj) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { > + RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; > + int bit = misa_cfg->misa_bit; > + > + misa_cfg->name = riscv_get_misa_ext_name(bit); > + misa_cfg->description = riscv_get_misa_ext_description(bit); > + > + object_property_add(cpu_obj, misa_cfg->name, "bool", > + cpu_get_misa_ext_cfg, > + cpu_set_misa_ext_cfg, > + NULL, (void *)misa_cfg); > + object_property_set_description(cpu_obj, misa_cfg->name, > + misa_cfg->description); > + object_property_set_bool(cpu_obj, misa_cfg->name, > + misa_cfg->enabled, NULL); > + } > +} > + > static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones