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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id r7-20020aa7cb87000000b0052996528b81sm655511edt.45.2023.08.31.04.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 04:10:01 -0700 (PDT) Date: Thu, 31 Aug 2023 13:10:00 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH 09/20] target/riscv/cpu.c: mark extensions arrays as 'const' Message-ID: <20230831-aad9959328ec3b97b5446930@orel> References: <20230825130853.511782-1-dbarboza@ventanamicro.com> <20230825130853.511782-10-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230825130853.511782-10-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 25, 2023 at 10:08:42AM -0300, Daniel Henrique Barboza wrote: > We'll need to export these arrays to the accelerator classes in the next > patches. Mark them as 'const' now to minimize changes in the future. Not to "minimize changes in the future", but "because they should not be modified at runtime". > > Note that 'riscv_cpu_options' will also be exported, but can't be marked > as 'const', because the properties are changed via > qdev_property_add_static(). > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 22 +++++++++++++--------- > 1 file changed, 13 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index dbf81796d2..4eda853f1d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1381,7 +1381,7 @@ typedef struct RISCVCPUMultiExtConfig { > {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ > .enabled = _defval} > > -static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > +static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), > @@ -1441,7 +1441,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > -static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > +static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), > MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), > MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), > @@ -1459,7 +1459,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > }; > > /* These are experimental so mark with 'x-' */ > -static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > +static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zicond", ext_zicond, false), > > /* ePMP 0.9.3 */ > @@ -1532,7 +1532,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, > } > > static void cpu_add_multi_ext_prop(Object *cpu_obj, > - RISCVCPUMultiExtConfig *multi_cfg) > + const RISCVCPUMultiExtConfig *multi_cfg) > { > object_property_add(cpu_obj, multi_cfg->name, "bool", > cpu_get_multi_ext_cfg, > @@ -1568,9 +1568,11 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, > #endif > > static void riscv_cpu_add_multiext_prop_array(Object *obj, > - RISCVCPUMultiExtConfig *array) > + const RISCVCPUMultiExtConfig *array) > { > - for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) { > + const RISCVCPUMultiExtConfig *prop; > + > + for (prop = array; prop && prop->name; prop++) { > cpu_add_multi_ext_prop(obj, prop); > } > } > @@ -1594,9 +1596,11 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) > } > > static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, > - RISCVCPUMultiExtConfig *array) > + const RISCVCPUMultiExtConfig *array) > { > - for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) { > + const RISCVCPUMultiExtConfig *prop; > + > + for (prop = array; prop && prop->name; prop++) { > riscv_cpu_add_kvm_unavail_prop(obj, prop->name); > } > } > @@ -1659,7 +1663,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) > { > RISCVCPU *cpu = RISCV_CPU(obj); > CPURISCVState *env = &cpu->env; > - RISCVCPUMultiExtConfig *prop; > + const RISCVCPUMultiExtConfig *prop; > > /* Enable RVG, RVJ and RVV that are disabled by default */ > set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); > -- > 2.41.0 > > Other than the commit message change, Reviewed-by: Andrew Jones