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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id qq7-20020a17090720c700b00992afee724bsm791795ejb.76.2023.08.31.07.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 07:05:32 -0700 (PDT) Date: Thu, 31 Aug 2023 16:05:31 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH RESEND v8 00/20] riscv: 'max' CPU, detect user choice in TCG Message-ID: <20230831-adf7386649250fe8c2af87c3@orel> References: <20230824221440.484675-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230824221440.484675-1-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::644; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 24, 2023 at 07:14:20PM -0300, Daniel Henrique Barboza wrote: > Hi, > > This is a resend of these two patch sets because they no longer apply > into Alistair's riscv-to-apply.next: > > [PATCH v8 00/12] riscv: add 'max' CPU, deprecate 'any' > https://lore.kernel.org/qemu-riscv/20230815223741.433763-1-dbarboza@ventanamicro.com/ > > [PATCH v3 0/8] riscv: detecting user choice in TCG extensions > https://lore.kernel.org/qemu-riscv/20230815224733.434682-1-dbarboza@ventanamicro.com/ > > > They're being sent in a single package for convenience. No other changes > made from their old versions aside from the rebase. > > Patches missing acks: 4,7,8 > > Changes from v7: > - patch 7: > - add riscv_cpu_add_qdev_prop_array() function instead of a macro > - patch 8: > - add riscv_cpu_add_kvm_unavail_prop_array() function instead of a > macro > - v7 link: https://lore.kernel.org/qemu-riscv/20230815201559.398643-1-dbarboza@ventanamicro.com/ > Tracking whether or not the user enabled/disabled an extension is good. I see we're still not tracking for the MISA extensions, though. If tracking isn't necessary for them, then a comment above riscv_cpu_add_misa_properties() explaining why not would be good. If tracking may be necessary, then making them consistent with the multi extensions by using the hash would be good. Thanks, drew