From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v2 10/14] tcg/loongarch64: Lower vector shift vector ops
Date: Fri, 1 Sep 2023 17:31:03 +0800 [thread overview]
Message-ID: <20230901093258.942357-11-c@jia.je> (raw)
In-Reply-To: <20230901093258.942357-1-c@jia.je>
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 24 ++++++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 1e587a82b1..9f02805c4b 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1683,6 +1683,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const LoongArchInsn ussub_vec_insn[4] = {
OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU
};
+ static const LoongArchInsn shlv_vec_insn[4] = {
+ OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D
+ };
+ static const LoongArchInsn shrv_vec_insn[4] = {
+ OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D
+ };
+ static const LoongArchInsn sarv_vec_insn[4] = {
+ OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D
+ };
a0 = args[0];
a1 = args[1];
@@ -1845,6 +1854,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ussub_vec:
tcg_out32(s, encode_vdvjvk_insn(ussub_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_shlv_vec:
+ tcg_out32(s, encode_vdvjvk_insn(shlv_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_shrv_vec:
+ tcg_out32(s, encode_vdvjvk_insn(shrv_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_sarv_vec:
+ tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1880,6 +1898,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_usadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
return 1;
default:
return 0;
@@ -2063,6 +2084,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_usadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 72bfd0d440..d27f3737ad 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -186,7 +186,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
--
2.42.0
next prev parent reply other threads:[~2023-09-01 9:35 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 9:30 [PATCH v2 00/14] Lower TCG vector ops to LSX Jiajie Chen
2023-09-01 9:30 ` [PATCH v2 01/14] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-01 17:06 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 02/14] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-01 17:05 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-01 17:24 ` Richard Henderson
2023-09-01 17:28 ` Jiajie Chen
2023-09-01 17:48 ` Richard Henderson
2023-09-02 1:06 ` Jiajie Chen
2023-09-01 9:30 ` [PATCH v2 04/14] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-01 17:58 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 05/14] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-01 17:59 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 06/14] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 07/14] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 08/14] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 09/14] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-01 9:31 ` Jiajie Chen [this message]
2023-09-01 9:31 ` [PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-01 18:01 ` Richard Henderson
2023-09-01 9:31 ` [PATCH v2 13/14] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-01 18:02 ` Richard Henderson
2023-09-01 9:31 ` [PATCH v2 14/14] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-01 18:06 ` Richard Henderson
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