qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
	git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops
Date: Fri,  1 Sep 2023 17:31:05 +0800	[thread overview]
Message-ID: <20230901093258.942357-13-c@jia.je> (raw)
In-Reply-To: <20230901093258.942357-1-c@jia.je>

Lower the following ops:

- shli_vec
- shrv_vec
- sarv_vec

Signed-off-by: Jiajie Chen <c@jia.je>
---
 tcg/loongarch64/tcg-target.c.inc | 21 +++++++++++++++++++++
 tcg/loongarch64/tcg-target.h     |  2 +-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 8de4c36396..ccb362205e 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1692,6 +1692,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     static const LoongArchInsn sarv_vec_insn[4] = {
         OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D
     };
+    static const LoongArchInsn shli_vec_insn[4] = {
+        OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D
+    };
+    static const LoongArchInsn shri_vec_insn[4] = {
+        OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D
+    };
+    static const LoongArchInsn sari_vec_insn[4] = {
+        OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D
+    };
 
     a0 = args[0];
     a1 = args[1];
@@ -1864,6 +1873,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sarv_vec:
         tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
         break;
+    case INDEX_op_shli_vec:
+        tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2));
+        break;
+    case INDEX_op_shri_vec:
+        tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2));
+        break;
+    case INDEX_op_sari_vec:
+        tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2));
+        break;
     case INDEX_op_bitsel_vec:
         /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
         tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
@@ -2097,6 +2115,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_not_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return C_O1_I1(w, w);
 
     case INDEX_op_bitsel_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index c77672d92c..b4dab03469 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -184,7 +184,7 @@ extern bool use_lsx_instructions;
 #define TCG_TARGET_HAS_nor_vec          1
 #define TCG_TARGET_HAS_eqv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
-#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
 #define TCG_TARGET_HAS_roti_vec         0
-- 
2.42.0



  parent reply	other threads:[~2023-09-01  9:35 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-01  9:30 [PATCH v2 00/14] Lower TCG vector ops to LSX Jiajie Chen
2023-09-01  9:30 ` [PATCH v2 01/14] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-01 17:06   ` Richard Henderson
2023-09-01  9:30 ` [PATCH v2 02/14] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-01 17:05   ` Richard Henderson
2023-09-01  9:30 ` [PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-01 17:24   ` Richard Henderson
2023-09-01 17:28     ` Jiajie Chen
2023-09-01 17:48       ` Richard Henderson
2023-09-02  1:06         ` Jiajie Chen
2023-09-01  9:30 ` [PATCH v2 04/14] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-01 17:58   ` Richard Henderson
2023-09-01  9:30 ` [PATCH v2 05/14] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-01 17:59   ` Richard Henderson
2023-09-01  9:30 ` [PATCH v2 06/14] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-01  9:31 ` [PATCH v2 07/14] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-01  9:31 ` [PATCH v2 08/14] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-01  9:31 ` [PATCH v2 09/14] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-01  9:31 ` [PATCH v2 10/14] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-01  9:31 ` [PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-01  9:31 ` Jiajie Chen [this message]
2023-09-01 18:01   ` [PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops Richard Henderson
2023-09-01  9:31 ` [PATCH v2 13/14] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-01 18:02   ` Richard Henderson
2023-09-01  9:31 ` [PATCH v2 14/14] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-01 18:06   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230901093258.942357-13-c@jia.je \
    --to=c@jia.je \
    --cc=gaosong@loongson.cn \
    --cc=git@xen0n.name \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).