From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v3 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Date: Sat, 2 Sep 2023 13:02:04 +0800 [thread overview]
Message-ID: <20230902050415.1832700-5-c@jia.je> (raw)
In-Reply-To: <20230902050415.1832700-1-c@jia.je>
Signed-off-by: Jiajie Chen <c@jia.je>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 37b3f80bf9..8c8ea5d919 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -31,4 +31,5 @@ C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, ri)
C_O1_I2(r, rZ, rJ)
C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, w, wM)
C_O1_I4(r, rZ, rJ, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h
index 81b8d40278..a8a1c44014 100644
--- a/tcg/loongarch64/tcg-target-con-str.h
+++ b/tcg/loongarch64/tcg-target-con-str.h
@@ -26,3 +26,4 @@ CONST('U', TCG_CT_CONST_U12)
CONST('Z', TCG_CT_CONST_ZERO)
CONST('C', TCG_CT_CONST_C12)
CONST('W', TCG_CT_CONST_WSZ)
+CONST('M', TCG_CT_CONST_VCMP)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 07a0326e5d..129dd92910 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -176,6 +176,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_CT_CONST_U12 0x800
#define TCG_CT_CONST_C12 0x1000
#define TCG_CT_CONST_WSZ 0x2000
+#define TCG_CT_CONST_VCMP 0x4000
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
@@ -209,6 +210,10 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
return true;
}
+ int64_t vec_val = sextract64(val, 0, 8 << vece);
+ if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) {
+ return true;
+ }
return false;
}
@@ -1624,6 +1629,23 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0, a1, a2;
TCGReg temp = TCG_REG_TMP0;
+ TCGReg temp_vec = TCG_VEC_TMP0;
+
+ static const LoongArchInsn cmp_vec_insn[16][4] = {
+ [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D},
+ [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D},
+ [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU},
+ [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D},
+ [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU},
+ };
+ static const LoongArchInsn cmp_vec_imm_insn[16][4] = {
+ [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D},
+ [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D},
+ [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU},
+ [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D},
+ [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU},
+ };
+ LoongArchInsn insn;
a0 = args[0];
a1 = args[1];
@@ -1651,6 +1673,45 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_vldx(s, a0, a1, temp);
}
break;
+ case INDEX_op_cmp_vec:
+ TCGCond cond = args[3];
+ if (const_args[2]) {
+ /*
+ * cmp_vec dest, src, value
+ * Try vseqi/vslei/vslti
+ */
+ int64_t value = sextract64(a2, 0, 8 << vece);
+ if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \
+ cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) {
+ tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \
+ a0, a1, value));
+ break;
+ } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) &&
+ (0x00 <= value && value <= 0x1f)) {
+ tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \
+ a0, a1, value));
+ break;
+ }
+
+ /*
+ * Fallback to:
+ * dupi_vec temp, a2
+ * cmp_vec a0, a1, temp, cond
+ */
+ tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
+ a2 = temp_vec;
+ }
+
+ insn = cmp_vec_insn[cond][vece];
+ if (insn == 0) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ insn = cmp_vec_insn[cond][vece];
+ tcg_debug_assert(insn != 0);
+ }
+ tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1666,6 +1727,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_st_vec:
case INDEX_op_dup_vec:
case INDEX_op_dupm_vec:
+ case INDEX_op_cmp_vec:
return 1;
default:
return 0;
@@ -1827,6 +1889,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_st_vec:
return C_O0_I2(w, r);
+ case INDEX_op_cmp_vec:
+ return C_O1_I2(w, w, wM);
+
default:
g_assert_not_reached();
}
--
2.42.0
next prev parent reply other threads:[~2023-09-02 5:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-02 5:02 [PATCH v3 00/16] Lower TCG vector ops to LSX Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 01/16] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 03/16] tcg: pass vece to tcg_target_const_match() Jiajie Chen
2023-09-03 0:50 ` Richard Henderson
2023-09-02 5:02 ` Jiajie Chen [this message]
2023-09-03 0:50 ` [PATCH v3 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Richard Henderson
2023-09-02 5:02 ` [PATCH v3 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-03 0:54 ` Richard Henderson
2023-09-02 5:02 ` [PATCH v3 06/16] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 07/16] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 08/16] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 09/16] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 10/16] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 11/16] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 13/16] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 15/16] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-02 5:02 ` [PATCH v3 16/16] tcg/loongarch64: Implement 128-bit load & store Jiajie Chen
2023-09-03 1:06 ` Richard Henderson
2023-09-03 1:10 ` Jiajie Chen
2023-09-04 1:43 ` gaosong
2023-09-04 9:43 ` bibo mao
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