From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v9 20/20] target/riscv/cpu.c: consider user option with RVG
Date: Mon, 4 Sep 2023 11:18:41 +0200 [thread overview]
Message-ID: <20230904-3492f3db40617b7780ed7861@orel> (raw)
In-Reply-To: <20230901194627.1214811-21-dbarboza@ventanamicro.com>
On Fri, Sep 01, 2023 at 04:46:26PM -0300, Daniel Henrique Barboza wrote:
> Enabling RVG will enable a set of extensions that we're not checking if
> the user was okay enabling or not. And in this case we want to error
> out, instead of ignoring, otherwise we will be inconsistent enabling RVG
> without all its extensions.
>
> After this patch, disabling ifencei or icsr while enabling RVG will
> result in error:
>
> $ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic
> qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 78382cb5f2..be1c028095 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1153,9 +1153,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
> riscv_has_ext(env, RVD) &&
> cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> +
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
> + !cpu->cfg.ext_icsr) {
> + error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
> + return;
> + }
> +
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
> + !cpu->cfg.ext_ifencei) {
> + error_setg(errp, "RVG requires Zifencei but user set "
> + "Zifencei to false");
> + return;
> + }
> +
> warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> - cpu->cfg.ext_icsr = true;
> - cpu->cfg.ext_ifencei = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
>
> env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
> env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> --
> 2.41.0
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-09-04 9:19 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 19:46 [PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 01/20] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 02/20] target/riscv/cpu.c: skip 'bool' check when filtering KVM props Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 03/20] target/riscv/cpu.c: split kvm prop handling to its own helper Daniel Henrique Barboza
2023-09-11 13:32 ` Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 04/20] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] Daniel Henrique Barboza
2023-09-04 1:48 ` Alistair Francis
2023-09-04 7:55 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 05/20] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 06/20] target/riscv/cpu.c: split vendor " Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 07/20] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() Daniel Henrique Barboza
2023-09-04 1:51 ` Alistair Francis
2023-09-04 7:59 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 08/20] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() Daniel Henrique Barboza
2023-09-04 2:15 ` Alistair Francis
2023-09-01 19:46 ` [PATCH v9 09/20] target/riscv/cpu.c: limit cfg->vext_spec log message Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 10/20] target/riscv: add 'max' CPU type Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 11/20] avocado, risc-v: add tuxboot tests for 'max' CPU Daniel Henrique Barboza
2023-09-04 8:22 ` Philippe Mathieu-Daudé
2023-09-07 3:47 ` Alistair Francis
2023-09-01 19:46 ` [PATCH v9 12/20] target/riscv: deprecate the 'any' CPU type Daniel Henrique Barboza
2023-09-04 8:23 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 13/20] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 14/20] target/riscv: make CPUCFG() macro public Daniel Henrique Barboza
2023-09-04 8:04 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-09-04 9:16 ` Andrew Jones
2023-09-07 4:06 ` Alistair Francis
2023-09-01 19:46 ` [PATCH v9 16/20] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 17/20] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 18/20] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 19/20] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 20/20] target/riscv/cpu.c: consider user option with RVG Daniel Henrique Barboza
2023-09-04 9:18 ` Andrew Jones [this message]
2023-09-07 4:13 ` [PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG Alistair Francis
2023-09-11 2:34 ` Alistair Francis
2023-09-11 9:10 ` Daniel Henrique Barboza
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