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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id w2-20020adff9c2000000b00317ddccb0d1sm13908274wrr.24.2023.09.04.02.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Sep 2023 02:18:42 -0700 (PDT) Date: Mon, 4 Sep 2023 11:18:41 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v9 20/20] target/riscv/cpu.c: consider user option with RVG Message-ID: <20230904-3492f3db40617b7780ed7861@orel> References: <20230901194627.1214811-1-dbarboza@ventanamicro.com> <20230901194627.1214811-21-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230901194627.1214811-21-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Sep 01, 2023 at 04:46:26PM -0300, Daniel Henrique Barboza wrote: > Enabling RVG will enable a set of extensions that we're not checking if > the user was okay enabling or not. And in this case we want to error > out, instead of ignoring, otherwise we will be inconsistent enabling RVG > without all its extensions. > > After this patch, disabling ifencei or icsr while enabling RVG will > result in error: > > $ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic > qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 78382cb5f2..be1c028095 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1153,9 +1153,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && > riscv_has_ext(env, RVD) && > cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > + > + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && > + !cpu->cfg.ext_icsr) { > + error_setg(errp, "RVG requires Zicsr but user set Zicsr to false"); > + return; > + } > + > + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && > + !cpu->cfg.ext_ifencei) { > + error_setg(errp, "RVG requires Zifencei but user set " > + "Zifencei to false"); > + return; > + } > + > warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > - cpu->cfg.ext_icsr = true; > - cpu->cfg.ext_ifencei = true; > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); > > env->misa_ext |= RVI | RVM | RVA | RVF | RVD; > env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; > -- > 2.41.0 > Reviewed-by: Andrew Jones