From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>,
Fan Ni <fan.ni@samsung.com>, <linux-cxl@vger.kernel.org>
Cc: "Li Zhijian" <lizhijian@cn.fujitsu.com>,
"Dave Jiang" <dave.jiang@intel.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
linuxarm@huawei.com
Subject: [PATCH 4/4] docs/cxl: Change to lowercase as others
Date: Mon, 4 Sep 2023 14:28:06 +0100 [thread overview]
Message-ID: <20230904132806.6094-5-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230904132806.6094-1-Jonathan.Cameron@huawei.com>
From: Li Zhijian <lizhijian@cn.fujitsu.com>
Using the same style as elsewhere for topology / topo
Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
Link: https://lore.kernel.org/r/20230519085802.2106900-2-lizhijian@cn.fujitsu.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
docs/system/devices/cxl.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f12011e230..b742120657 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs
and exposing those via normal memory configurations as would be done
for system RAM.
-Example system Topology. x marks the match in each decoder level::
+Example system topology. x marks the match in each decoder level::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
@@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level::
___________|___ __________|__ __|_________ ___|_________
(3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
| Appears in | | Appears in | | Appears in | | Appear in |
- | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
- | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
+ | PCI topology | | PCI topology| | PCI topo | | PCI topo |
+ | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
|_______________| |_____________| |____________| |_____________|
| | | |
| | | |
@@ -272,7 +272,7 @@ Example topology involving a switch::
| Root Port 0 |
| Appears in |
| PCI topology |
- | As 0c:00.0 |
+ | as 0c:00.0 |
|___________x___|
|
|
--
2.39.2
next prev parent reply other threads:[~2023-09-04 13:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-04 13:28 [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup Jonathan Cameron via
2023-09-04 13:28 ` [PATCH 1/4] hw/cxl: Fix CFMW config memory leak Jonathan Cameron via
2023-09-12 21:22 ` Fan Ni
2023-09-13 13:59 ` Michael Tokarev
2023-09-04 13:28 ` [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS Jonathan Cameron via
2023-09-04 13:45 ` Philippe Mathieu-Daudé
2023-09-12 21:23 ` Fan Ni
2023-09-22 20:08 ` Michael Tokarev
2023-09-22 20:59 ` Dave Jiang
2023-09-04 13:28 ` [PATCH 3/4] hw/cxl/cxl_device: Replace magic number in CXLError definition Jonathan Cameron via
2023-09-04 13:46 ` Philippe Mathieu-Daudé
2023-09-04 13:28 ` Jonathan Cameron via [this message]
2023-09-04 13:46 ` [PATCH 4/4] docs/cxl: Change to lowercase as others Philippe Mathieu-Daudé
2023-09-12 21:26 ` Fan Ni
2023-09-13 6:38 ` [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup Philippe Mathieu-Daudé
2023-09-13 14:00 ` Michael Tokarev
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