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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id o12-20020a5d408c000000b003142ea7a661sm1500224wrp.21.2023.09.08.01.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 01:42:02 -0700 (PDT) Date: Fri, 8 Sep 2023 10:42:01 +0200 From: Andrew Jones To: Michael Tokarev Cc: Colton Lewis , qemu-devel@nongnu.org, Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Andrew Jones , qemu-trivial@nongnu.org, qemu-stable Subject: Re: [PATCH] arm64: Restore trapless ptimer access Message-ID: <20230908-c42425ed51b75d247052cfde@orel> References: <20230831190052.129045-1-coltonlewis@google.com> <7d3615d0-d501-a28c-eebc-b3f7a599fc23@tls.msk.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7d3615d0-d501-a28c-eebc-b3f7a599fc23@tls.msk.ru> Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Sep 07, 2023 at 10:31:20PM +0300, Michael Tokarev wrote: > 31.08.2023 22:00, Colton Lewis wrote: > > Due to recent KVM changes, QEMU is setting a ptimer offset resulting > > in unintended trap and emulate access and a consequent performance > > hit. Filter out the PTIMER_CNT register to restore trapless ptimer > > access. > > > > Quoting Andrew Jones: > > > > Simply reading the CNT register and writing back the same value is > > enough to set an offset, since the timer will have certainly moved > > past whatever value was read by the time it's written. QEMU > > frequently saves and restores all registers in the get-reg-list array, > > unless they've been explicitly filtered out (with Linux commit > > 680232a94c12, KVM_REG_ARM_PTIMER_CNT is now in the array). So, to > > restore trapless ptimer accesses, we need a QEMU patch to filter out > > the register. > > > > See > > https://lore.kernel.org/kvmarm/gsntttsonus5.fsf@coltonlewis-kvm.c.googlers.com/T/#m0770023762a821db2a3f0dd0a7dc6aa54e0d0da9 > > for additional context. > > > > Signed-off-by: Andrew Jones > > --- > > target/arm/kvm64.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c > > index 4d904a1d11..2dd46e0a99 100644 > > --- a/target/arm/kvm64.c > > +++ b/target/arm/kvm64.c > > @@ -672,6 +672,7 @@ typedef struct CPRegStateLevel { > > */ > > static const CPRegStateLevel non_runtime_cpregs[] = { > > { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE }, > > + { KVM_REG_ARM_PTIMER_CNT, KVM_PUT_FULL_STATE }, > > }; > > int kvm_arm_cpreg_level(uint64_t regidx) > > While this patch itself is one-liner and trivial and all, I'd rather > not apply this to the trivial-patches tree, - it requires a little > bit more than trivial expertise in this area. > > So basically, ping for qemu-arm@ ? :) > I agree that qemu-trivial should not have been CC'ed for this patch. Thanks, drew