From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v4 09/16] tcg/loongarch64: Lower vector min max ops
Date: Fri, 8 Sep 2023 10:21:16 +0800 [thread overview]
Message-ID: <20230908022302.180442-10-c@jia.je> (raw)
In-Reply-To: <20230908022302.180442-1-c@jia.je>
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 0814f62905..bdf22d8807 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1701,6 +1701,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const LoongArchInsn mul_vec_insn[4] = {
OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D
};
+ static const LoongArchInsn smin_vec_insn[4] = {
+ OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D
+ };
+ static const LoongArchInsn umin_vec_insn[4] = {
+ OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU
+ };
+ static const LoongArchInsn smax_vec_insn[4] = {
+ OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D
+ };
+ static const LoongArchInsn umax_vec_insn[4] = {
+ OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU
+ };
a0 = args[0];
a1 = args[1];
@@ -1805,6 +1817,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mul_vec:
tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_smin_vec:
+ tcg_out32(s, encode_vdvjvk_insn(smin_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_smax_vec:
+ tcg_out32(s, encode_vdvjvk_insn(smax_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_umin_vec:
+ tcg_out32(s, encode_vdvjvk_insn(umin_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_umax_vec:
+ tcg_out32(s, encode_vdvjvk_insn(umax_vec_insn[vece], a0, a1, a2));
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1832,6 +1856,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
case INDEX_op_mul_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_umax_vec:
return 1;
default:
return 0;
@@ -2007,6 +2035,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_xor_vec:
case INDEX_op_nor_vec:
case INDEX_op_mul_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_umax_vec:
return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 2c2266ed31..ec725aaeaa 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -193,7 +193,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_sat_vec 0
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
--
2.42.0
next prev parent reply other threads:[~2023-09-08 2:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 2:21 [PATCH v4 00/16] Lower TCG vector ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 01/16] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 03/16] tcg: pass vece to tcg_target_const_match() Jiajie Chen
2023-09-08 7:36 ` Philippe Mathieu-Daudé
2023-09-08 2:21 ` [PATCH v4 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-09 21:49 ` Richard Henderson
2023-09-08 2:21 ` [PATCH v4 06/16] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 07/16] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 08/16] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-08 2:21 ` Jiajie Chen [this message]
2023-09-08 2:21 ` [PATCH v4 10/16] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 11/16] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 13/16] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 15/16] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 16/16] tcg/loongarch64: Implement 128-bit load & store Jiajie Chen
2023-09-09 21:56 ` Richard Henderson
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