From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v4 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel
Date: Fri, 8 Sep 2023 10:21:19 +0800 [thread overview]
Message-ID: <20230908022302.180442-13-c@jia.je> (raw)
In-Reply-To: <20230908022302.180442-1-c@jia.je>
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++++++++++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 3f530ad4d8..914572d21b 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -35,4 +35,5 @@ C_O1_I2(r, rZ, rZ)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wM)
C_O1_I2(w, w, wA)
+C_O1_I3(w, w, w, w)
C_O1_I4(r, rZ, rJ, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 6958fd219c..a33ec594ee 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1676,7 +1676,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const int const_args[TCG_MAX_OP_ARGS])
{
TCGType type = vecl + TCG_TYPE_V64;
- TCGArg a0, a1, a2;
+ TCGArg a0, a1, a2, a3;
TCGReg temp = TCG_REG_TMP0;
TCGReg temp_vec = TCG_VEC_TMP0;
@@ -1738,6 +1738,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
a0 = args[0];
a1 = args[1];
a2 = args[2];
+ a3 = args[3];
/* Currently only supports V128 */
tcg_debug_assert(type == TCG_TYPE_V128);
@@ -1871,6 +1872,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_bitsel_vec:
+ /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
+ tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1909,6 +1914,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_bitsel_vec:
return 1;
default:
return 0;
@@ -2101,6 +2107,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_neg_vec:
return C_O1_I1(w, w);
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(w, w, w, w);
+
default:
g_assert_not_reached();
}
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 7e9fb61c47..bc56939a57 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -194,7 +194,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
--
2.42.0
next prev parent reply other threads:[~2023-09-08 2:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 2:21 [PATCH v4 00/16] Lower TCG vector ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 01/16] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 03/16] tcg: pass vece to tcg_target_const_match() Jiajie Chen
2023-09-08 7:36 ` Philippe Mathieu-Daudé
2023-09-08 2:21 ` [PATCH v4 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-09 21:49 ` Richard Henderson
2023-09-08 2:21 ` [PATCH v4 06/16] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 07/16] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 08/16] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 09/16] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 10/16] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 11/16] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-08 2:21 ` Jiajie Chen [this message]
2023-09-08 2:21 ` [PATCH v4 13/16] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 15/16] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 16/16] tcg/loongarch64: Implement 128-bit load & store Jiajie Chen
2023-09-09 21:56 ` Richard Henderson
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