From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v4 13/16] tcg/loongarch64: Lower vector shift integer ops
Date: Fri, 8 Sep 2023 10:21:20 +0800 [thread overview]
Message-ID: <20230908022302.180442-14-c@jia.je> (raw)
In-Reply-To: <20230908022302.180442-1-c@jia.je>
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 21 +++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index a33ec594ee..c21c917083 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1734,6 +1734,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const LoongArchInsn sarv_vec_insn[4] = {
OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D
};
+ static const LoongArchInsn shli_vec_insn[4] = {
+ OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D
+ };
+ static const LoongArchInsn shri_vec_insn[4] = {
+ OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D
+ };
+ static const LoongArchInsn sari_vec_insn[4] = {
+ OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D
+ };
a0 = args[0];
a1 = args[1];
@@ -1872,6 +1881,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_shli_vec:
+ tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_shri_vec:
+ tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2));
+ break;
+ case INDEX_op_sari_vec:
+ tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2));
+ break;
case INDEX_op_bitsel_vec:
/* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
@@ -2105,6 +2123,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
return C_O1_I1(w, w);
case INDEX_op_bitsel_vec:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index bc56939a57..d7b806e252 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -186,7 +186,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_nor_vec 1
#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_mul_vec 1
-#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_roti_vec 0
--
2.42.0
next prev parent reply other threads:[~2023-09-08 2:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 2:21 [PATCH v4 00/16] Lower TCG vector ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 01/16] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 03/16] tcg: pass vece to tcg_target_const_match() Jiajie Chen
2023-09-08 7:36 ` Philippe Mathieu-Daudé
2023-09-08 2:21 ` [PATCH v4 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-09 21:49 ` Richard Henderson
2023-09-08 2:21 ` [PATCH v4 06/16] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 07/16] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 08/16] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 09/16] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 10/16] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 11/16] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-08 2:21 ` Jiajie Chen [this message]
2023-09-08 2:21 ` [PATCH v4 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 15/16] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 16/16] tcg/loongarch64: Implement 128-bit load & store Jiajie Chen
2023-09-09 21:56 ` Richard Henderson
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