From: Jiajie Chen <c@jia.je>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
git@xen0n.name, Jiajie Chen <c@jia.je>
Subject: [PATCH v4 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub
Date: Fri, 8 Sep 2023 10:21:12 +0800 [thread overview]
Message-ID: <20230908022302.180442-6-c@jia.je> (raw)
In-Reply-To: <20230908022302.180442-1-c@jia.je>
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen <c@jia.je>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 61 ++++++++++++++++++++++++++++
3 files changed, 63 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 8c8ea5d919..2d5dce75c3 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -32,4 +32,5 @@ C_O1_I2(r, rZ, ri)
C_O1_I2(r, rZ, rJ)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, w, wM)
+C_O1_I2(w, w, wA)
C_O1_I4(r, rZ, rJ, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h
index a8a1c44014..2ba9c135ac 100644
--- a/tcg/loongarch64/tcg-target-con-str.h
+++ b/tcg/loongarch64/tcg-target-con-str.h
@@ -27,3 +27,4 @@ CONST('Z', TCG_CT_CONST_ZERO)
CONST('C', TCG_CT_CONST_C12)
CONST('W', TCG_CT_CONST_WSZ)
CONST('M', TCG_CT_CONST_VCMP)
+CONST('A', TCG_CT_CONST_VADD)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 129dd92910..1a369b237c 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -177,6 +177,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_CT_CONST_C12 0x1000
#define TCG_CT_CONST_WSZ 0x2000
#define TCG_CT_CONST_VCMP 0x4000
+#define TCG_CT_CONST_VADD 0x8000
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
@@ -214,6 +215,9 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) {
return true;
}
+ if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) {
+ return true;
+ }
return false;
}
@@ -1621,6 +1625,51 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
}
}
+static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0,
+ const TCGArg a1, const TCGArg a2,
+ bool a2_is_const, bool is_add)
+{
+ static const LoongArchInsn add_vec_insn[4] = {
+ OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D
+ };
+ static const LoongArchInsn add_vec_imm_insn[4] = {
+ OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU
+ };
+ static const LoongArchInsn sub_vec_insn[4] = {
+ OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D
+ };
+ static const LoongArchInsn sub_vec_imm_insn[4] = {
+ OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU
+ };
+
+ if (a2_is_const) {
+ int64_t value = sextract64(a2, 0, 8 << vece);
+ if (!is_add) {
+ value = -value;
+ }
+
+ /* Try vaddi/vsubi */
+ if (0 <= value && value <= 0x1f) {
+ tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \
+ a1, value));
+ return;
+ } else if (-0x1f <= value && value < 0) {
+ tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \
+ a1, -value));
+ return;
+ }
+
+ /* constraint TCG_CT_CONST_VADD ensures unreachable */
+ g_assert_not_reached();
+ }
+
+ if (is_add) {
+ tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2));
+ } else {
+ tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2));
+ }
+}
+
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
unsigned vecl, unsigned vece,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1712,6 +1761,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
break;
+ case INDEX_op_add_vec:
+ tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true);
+ break;
+ case INDEX_op_sub_vec:
+ tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false);
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1728,6 +1783,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_dup_vec:
case INDEX_op_dupm_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
return 1;
default:
return 0;
@@ -1892,6 +1949,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_cmp_vec:
return C_O1_I2(w, w, wM);
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ return C_O1_I2(w, w, wA);
+
default:
g_assert_not_reached();
}
--
2.42.0
next prev parent reply other threads:[~2023-09-08 2:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 2:21 [PATCH v4 00/16] Lower TCG vector ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 01/16] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 03/16] tcg: pass vece to tcg_target_const_match() Jiajie Chen
2023-09-08 7:36 ` Philippe Mathieu-Daudé
2023-09-08 2:21 ` [PATCH v4 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-08 2:21 ` Jiajie Chen [this message]
2023-09-09 21:49 ` [PATCH v4 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Richard Henderson
2023-09-08 2:21 ` [PATCH v4 06/16] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 07/16] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 08/16] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 09/16] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 10/16] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 11/16] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 13/16] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 15/16] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-08 2:21 ` [PATCH v4 16/16] tcg/loongarch64: Implement 128-bit load & store Jiajie Chen
2023-09-09 21:56 ` Richard Henderson
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