[PATCH] qemu/timer: Add host ticks function for RISC-V

[LIU Zhiwei <zhiwei_liu@linux.alibaba.com>]

From: LIU Zhiwei <lzw194868@alibaba-inc.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 include/qemu/timer.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 9a91cb1248..ce0b66d122 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -979,6 +979,25 @@ static inline int64_t cpu_get_host_ticks(void)
     return cur - ofs;
 }
 
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32
+static inline int64_t cpu_get_host_ticks(void)
+{
+    uint32_t lo, hi;
+    asm volatile("RDCYCLE %0\n\t"
+                 "RDCYCLEH %1"
+                 : "=r"(lo), "=r"(hi));
+    return lo | (uint64_t)hi << 32;
+}
+
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen > 32
+static inline int64_t cpu_get_host_ticks(void)
+{
+    int64_t val;
+
+    asm volatile("RDCYCLE %0" : "=r"(cc));
+    return val;
+}
+
 #else
 /* The host CPU doesn't have an easily accessible cycle counter.
    Just return a monotonically increasing value.  This will be
-- 
2.17.1