[RESEND] qemu/timer: Add host ticks function for RISC-V

[RESEND] qemu/timer: Add host ticks function for RISC-V

[LIU Zhiwei]

From: LIU Zhiwei <lzw194868@alibaba-inc.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 include/qemu/timer.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 9a91cb1248..105767c195 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -979,6 +979,25 @@ static inline int64_t cpu_get_host_ticks(void)
     return cur - ofs;
 }
 
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32
+static inline int64_t cpu_get_host_ticks(void)
+{
+    uint32_t lo, hi;
+    asm volatile("RDCYCLE %0\n\t"
+                 "RDCYCLEH %1"
+                 : "=r"(lo), "=r"(hi));
+    return lo | (uint64_t)hi << 32;
+}
+
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen > 32
+static inline int64_t cpu_get_host_ticks(void)
+{
+    int64_t val;
+
+    asm volatile("RDCYCLE %0" : "=r"(val));
+    return val;
+}
+
 #else
 /* The host CPU doesn't have an easily accessible cycle counter.
    Just return a monotonically increasing value.  This will be
-- 
2.17.1

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

[Paolo Bonzini]

Queued, thanks.

Paolo

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

[Atish Patra]

On Thu, Sep 7, 2023 at 8:33 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: LIU Zhiwei <lzw194868@alibaba-inc.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>  include/qemu/timer.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/include/qemu/timer.h b/include/qemu/timer.h
> index 9a91cb1248..105767c195 100644
> --- a/include/qemu/timer.h
> +++ b/include/qemu/timer.h
> @@ -979,6 +979,25 @@ static inline int64_t cpu_get_host_ticks(void)
>      return cur - ofs;
>  }
>
> +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32
> +static inline int64_t cpu_get_host_ticks(void)
> +{
> +    uint32_t lo, hi;
> +    asm volatile("RDCYCLE %0\n\t"
> +                 "RDCYCLEH %1"
> +                 : "=r"(lo), "=r"(hi));
> +    return lo | (uint64_t)hi << 32;
> +}
> +
> +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen > 32
> +static inline int64_t cpu_get_host_ticks(void)
> +{
> +    int64_t val;
> +
> +    asm volatile("RDCYCLE %0" : "=r"(val));
> +    return val;
> +}
> +

rdcycle won't be accessible from the user space directly in the
future. rdcycle will be accessible via perf similar to other
architectures from the next kernel release [1].

rdtime must be used to compute the host ticks if the host is a riscv.
This is the equivalent of rdtsc in x86.

[1] https://lore.kernel.org/lkml/CAP-5=fVcMg7TL6W_jH61PW6dYMobuTs13d4JDuTAx=mxJ+PNtQ@mail.gmail.com/T/#md852c28f4070212973b796c232ecd37dc1c6cb2b

>  #else
>  /* The host CPU doesn't have an easily accessible cycle counter.
>     Just return a monotonically increasing value.  This will be
> --
> 2.17.1
>
>


-- 
Regards,
Atish

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

[Atish Patra]

On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Queued, thanks.
>

I didn't realize it was already queued. Gmail threads failed me this time.
@Paolo Bonzini : Can you please drop this one as this will break as
soon as the host riscv system
has the latest kernel ? I have provided more details in the original thread.

https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html

> Paolo
>
>


-- 
Regards,
Atish

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

[Paolo Bonzini]

[-- Attachment #1: Type: text/plain, Size: 880 bytes --]

Il sab 9 set 2023, 03:35 Atish Patra <atishp@atishpatra.org> ha scritto:

> On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
> >
> > Queued, thanks.
> >
>
> I didn't realize it was already queued. Gmail threads failed me this time.
> @Paolo Bonzini : Can you please drop this one as this will break as
> soon as the host riscv system
> has the latest kernel ? I have provided more details in the original
> thread.
>
> https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html


If you have dynamic clock adjustment, does rdcycle increase with a fixed
frequency or does it provide the raw number of clock cycles? If the latter,
I agree that it should be provided by perf; but if the frequency is fixed
then it would be the same as rdtsc on Intel.

Paolo


>
> > Paolo
> >
> >
>
>
> --
> Regards,
> Atish
>
>

[-- Attachment #2: Type: text/html, Size: 1702 bytes --]

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

[Palmer Dabbelt]

On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonzini@redhat.com wrote:
> Il sab 9 set 2023, 03:35 Atish Patra <atishp@atishpatra.org> ha scritto:
>
>> On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
>> >
>> > Queued, thanks.
>> >
>>
>> I didn't realize it was already queued. Gmail threads failed me this time.
>> @Paolo Bonzini : Can you please drop this one as this will break as
>> soon as the host riscv system
>> has the latest kernel ? I have provided more details in the original
>> thread.
>>
>> https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html
>
>
> If you have dynamic clock adjustment, does rdcycle increase with a fixed
> frequency or does it provide the raw number of clock cycles? If the latter,
> I agree that it should be provided by perf; but if the frequency is fixed
> then it would be the same as rdtsc on Intel.

That really depends on exactly how the system is set up, but there are 
systems for which the rdcycle frequency changes when clock speeds change 
and thus will produce surprising answers for users trying to use rdcycle 
as a RTC.  We have rdtime for that, but it has other problems (it's 
trapped and emulated in M-mode on some systems, so it's slow and noisy).

So we're steering folks towards perf where we can, as at least that way 
we've got a higher-level interface we can use to describe these quirks.

>
> Paolo
>
>
>>
>> > Paolo
>> >
>> >
>>
>>
>> --
>> Regards,
>> Atish
>>
>>

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

[LIU Zhiwei]

On 2023/9/9 22:45, Palmer Dabbelt wrote:
> On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonzini@redhat.com wrote:
>> Il sab 9 set 2023, 03:35 Atish Patra <atishp@atishpatra.org> ha scritto:
>>
>>> On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini <pbonzini@redhat.com> 
>>> wrote:
>>> >
>>> > Queued, thanks.
>>> >
>>>
>>> I didn't realize it was already queued. Gmail threads failed me this 
>>> time.
>>> @Paolo Bonzini : Can you please drop this one as this will break as
>>> soon as the host riscv system
>>> has the latest kernel ? I have provided more details in the original
>>> thread.
>>>
>>> https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html
>>
>>
>> If you have dynamic clock adjustment, does rdcycle increase with a fixed
>> frequency or does it provide the raw number of clock cycles? If the 
>> latter,
>> I agree that it should be provided by perf; but if the frequency is 
>> fixed
>> then it would be the same as rdtsc on Intel.
>
> That really depends on exactly how the system is set up, but there are 
> systems for which the rdcycle frequency changes when clock speeds 
> change and thus will produce surprising answers for users trying to 
> use rdcycle as a RTC.  We have rdtime for that, but it has other 
> problems (it's trapped and emulated in M-mode on some systems, so it's 
> slow and noisy).
>
> So we're steering folks towards perf where we can, as at least that 
> way we've got a higher-level interface we can use to describe these 
> quirks.

OK. I will send a v2 patch using rdtime.

Thanks,
Zhiwei

>
>>
>> Paolo
>>
>>
>>>
>>> > Paolo
>>> >
>>> >
>>>
>>>
>>> -- 
>>> Regards,
>>> Atish
>>>
>>>