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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/26] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
Date: Fri,  8 Sep 2023 18:05:40 +0100	[thread overview]
Message-ID: <20230908170557.773048-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230908170557.773048-1-peter.maydell@linaro.org>

From: Aaron Lindsay <aaron@os.amperecomputing.com>

Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-10-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-8-aaron@os.amperecomputing.com>
[rth: Simplify fpac comparison, reusing cmp_mask]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst |  2 ++
 target/arm/syndrome.h         |  7 +++++++
 target/arm/tcg/cpu64.c        |  2 +-
 target/arm/tcg/pauth_helper.c | 18 +++++++++++++++++-
 4 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index b5a667527b5..305b36b19e7 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -35,6 +35,8 @@ the following architecture extensions:
 - FEAT_FGT (Fine-Grained Traps)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
 - FEAT_FP16 (Half-precision floating-point data processing)
+- FEAT_FPAC (Faulting on AUT* instructions)
+- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
 - FEAT_FRINTTS (Floating-point to integer instructions)
 - FEAT_FlagM (Flag manipulation instructions v2)
 - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 62254d0e518..8a6b8f8162a 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -49,6 +49,7 @@ enum arm_exception_class {
     EC_SYSTEMREGISTERTRAP     = 0x18,
     EC_SVEACCESSTRAP          = 0x19,
     EC_ERETTRAP               = 0x1a,
+    EC_PACFAIL                = 0x1c,
     EC_SMETRAP                = 0x1d,
     EC_GPC                    = 0x1e,
     EC_INSNABORT              = 0x20,
@@ -232,6 +233,12 @@ static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
         | (is_16bit ? 0 : ARM_EL_IL) | etype;
 }
 
+static inline uint32_t syn_pacfail(bool data, int keynumber)
+{
+    int error_code = (data << 1) | keynumber;
+    return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code;
+}
+
 static inline uint32_t syn_pactrap(void)
 {
     return EC_PACTRAP << ARM_EL_EC_SHIFT;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index be103702505..ef222da57d4 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -803,7 +803,7 @@ void aarch64_max_tcg_initfn(Object *obj)
 
     t = cpu->isar.id_aa64isar1;
     t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
-    t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_2);
+    t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED);
     t = FIELD_DP64(t, ID_AA64ISAR1, API, 1);
     t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
     t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index c05c5b30ff9..4da2962ad5b 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -396,6 +396,14 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
     }
 }
 
+static G_NORETURN
+void pauth_fail_exception(CPUARMState *env, bool data,
+                          int keynumber, uintptr_t ra)
+{
+    raise_exception_ra(env, EXCP_UDEF, syn_pacfail(data, keynumber),
+                       exception_target_el(env), ra);
+}
+
 static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
                            ARMPACKey *key, bool data, int keynumber,
                            uintptr_t ra, bool is_combined)
@@ -416,7 +424,15 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
     cmp_mask &= ~MAKE_64BIT_MASK(55, 1);
 
     if (pauth_feature >= PauthFeat_2) {
-        return ptr ^ (pac & cmp_mask);
+        ARMPauthFeature fault_feature =
+            is_combined ? PauthFeat_FPACCOMBINED : PauthFeat_FPAC;
+        uint64_t result = ptr ^ (pac & cmp_mask);
+
+        if (pauth_feature >= fault_feature
+            && ((result ^ sextract64(result, 55, 1)) & cmp_mask)) {
+            pauth_fail_exception(env, data, keynumber, ra);
+        }
+        return result;
     }
 
     if ((pac ^ ptr) & cmp_mask) {
-- 
2.34.1



  parent reply	other threads:[~2023-09-08 17:07 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-08 17:05 [PULL 00/26] target-arm queue Peter Maydell
2023-09-08 17:05 ` [PULL 01/26] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC Peter Maydell
2023-09-08 17:05 ` [PULL 02/26] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
2023-09-08 17:05 ` [PULL 03/26] target/arm: Add feature detection for FEAT_Pauth2 and extensions Peter Maydell
2023-09-08 17:05 ` [PULL 04/26] target/arm: Don't change pauth features when changing algorithm Peter Maydell
2023-09-08 17:05 ` [PULL 05/26] target/arm: Implement FEAT_PACQARMA3 Peter Maydell
2023-09-08 17:05 ` [PULL 06/26] target/arm: Implement FEAT_EPAC Peter Maydell
2023-09-08 17:05 ` [PULL 07/26] target/arm: Implement FEAT_Pauth2 Peter Maydell
2023-09-08 17:05 ` [PULL 08/26] target/arm: Inform helpers whether a PAC instruction is 'combined' Peter Maydell
2023-09-08 17:05 ` Peter Maydell [this message]
2023-09-08 17:05 ` [PULL 10/26] hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte() Peter Maydell
2023-09-08 17:05 ` [PULL 11/26] hw/misc: Introduce the Xilinx CFI interface Peter Maydell
2023-09-08 17:05 ` [PULL 12/26] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Peter Maydell
2023-09-08 17:05 ` [PULL 13/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Peter Maydell
2023-09-08 17:05 ` [PULL 14/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Peter Maydell
2023-09-08 17:05 ` [PULL 15/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Peter Maydell
2023-09-08 17:05 ` [PULL 16/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Peter Maydell
2023-09-08 17:05 ` [PULL 17/26] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR Peter Maydell
2023-09-08 17:05 ` [PULL 18/26] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Peter Maydell
2023-09-08 17:05 ` [PULL 19/26] target/arm: Do not use gen_mte_checkN in trans_STGP Peter Maydell
2023-09-08 17:05 ` [PULL 20/26] arm64: Restore trapless ptimer access Peter Maydell
2023-09-08 17:05 ` [PULL 21/26] target/arm: Implement RMR_ELx Peter Maydell
2023-09-08 17:05 ` [PULL 22/26] target/arm: Implement cortex-a710 Peter Maydell
2023-09-08 17:05 ` [PULL 23/26] target/arm: Implement HCR_EL2.TIDCP Peter Maydell
2023-09-08 17:05 ` [PULL 24/26] target/arm: Implement FEAT_TIDCP1 Peter Maydell
2023-09-08 17:05 ` [PULL 25/26] target/arm: Enable SCTLR_EL1.TIDCP for user-only Peter Maydell
2023-09-08 17:05 ` [PULL 26/26] arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE Peter Maydell
2023-09-11 15:19 ` [PULL 00/26] target-arm queue Stefan Hajnoczi

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