From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/26] hw/misc: Introduce the Xilinx CFI interface
Date: Fri, 8 Sep 2023 18:05:42 +0100 [thread overview]
Message-ID: <20230908170557.773048-12-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230908170557.773048-1-peter.maydell@linaro.org>
From: Francisco Iglesias <francisco.iglesias@amd.com>
Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting
CFI data packets between the Xilinx Configuration Frame Unit models
(CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG)
and the Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20230831165701.2016397-2-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 6 ++++
include/hw/misc/xlnx-cfi-if.h | 59 +++++++++++++++++++++++++++++++++++
hw/misc/xlnx-cfi-if.c | 34 ++++++++++++++++++++
hw/misc/meson.build | 1 +
4 files changed, 100 insertions(+)
create mode 100644 include/hw/misc/xlnx-cfi-if.h
create mode 100644 hw/misc/xlnx-cfi-if.c
diff --git a/MAINTAINERS b/MAINTAINERS
index b471973e1e1..4b9512eda93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1026,6 +1026,12 @@ S: Maintained
F: hw/ssi/xlnx-versal-ospi.c
F: include/hw/ssi/xlnx-versal-ospi.h
+Xilinx Versal CFI
+M: Francisco Iglesias <francisco.iglesias@amd.com>
+S: Maintained
+F: hw/misc/xlnx-cfi-if.c
+F: include/hw/misc/xlnx-cfi-if.h
+
STM32F100
M: Alexandre Iooss <erdnaxe@crans.org>
L: qemu-arm@nongnu.org
diff --git a/include/hw/misc/xlnx-cfi-if.h b/include/hw/misc/xlnx-cfi-if.h
new file mode 100644
index 00000000000..f9bd12292d4
--- /dev/null
+++ b/include/hw/misc/xlnx-cfi-if.h
@@ -0,0 +1,59 @@
+/*
+ * Xilinx CFI interface
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef XLNX_CFI_IF_H
+#define XLNX_CFI_IF_H 1
+
+#include "qemu/help-texts.h"
+#include "hw/hw.h"
+#include "qom/object.h"
+
+#define TYPE_XLNX_CFI_IF "xlnx-cfi-if"
+typedef struct XlnxCfiIfClass XlnxCfiIfClass;
+DECLARE_CLASS_CHECKERS(XlnxCfiIfClass, XLNX_CFI_IF, TYPE_XLNX_CFI_IF)
+
+#define XLNX_CFI_IF(obj) \
+ INTERFACE_CHECK(XlnxCfiIf, (obj), TYPE_XLNX_CFI_IF)
+
+typedef enum {
+ PACKET_TYPE_CFU = 0x52,
+ PACKET_TYPE_CFRAME = 0xA1,
+} xlnx_cfi_packet_type;
+
+typedef enum {
+ CFRAME_FAR = 1,
+ CFRAME_SFR = 2,
+ CFRAME_FDRI = 4,
+ CFRAME_CMD = 6,
+} xlnx_cfi_reg_addr;
+
+typedef struct XlnxCfiPacket {
+ uint8_t reg_addr;
+ uint32_t data[4];
+} XlnxCfiPacket;
+
+typedef struct XlnxCfiIf {
+ Object Parent;
+} XlnxCfiIf;
+
+typedef struct XlnxCfiIfClass {
+ InterfaceClass parent;
+
+ void (*cfi_transfer_packet)(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
+} XlnxCfiIfClass;
+
+/**
+ * Transfer a XlnxCfiPacket.
+ *
+ * @cfi_if: the object implementing this interface
+ * @XlnxCfiPacket: a pointer to the XlnxCfiPacket to transfer
+ */
+void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
+
+#endif /* XLNX_CFI_IF_H */
diff --git a/hw/misc/xlnx-cfi-if.c b/hw/misc/xlnx-cfi-if.c
new file mode 100644
index 00000000000..c45f05c4aac
--- /dev/null
+++ b/hw/misc/xlnx-cfi-if.c
@@ -0,0 +1,34 @@
+/*
+ * Xilinx CFI interface
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "hw/misc/xlnx-cfi-if.h"
+
+void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
+{
+ XlnxCfiIfClass *xcic = XLNX_CFI_IF_GET_CLASS(cfi_if);
+
+ if (xcic->cfi_transfer_packet) {
+ xcic->cfi_transfer_packet(cfi_if, pkt);
+ }
+}
+
+static const TypeInfo xlnx_cfi_if_info = {
+ .name = TYPE_XLNX_CFI_IF,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XlnxCfiIfClass),
+};
+
+static void xlnx_cfi_if_register_types(void)
+{
+ type_register_static(&xlnx_cfi_if_info);
+}
+
+type_init(xlnx_cfi_if_register_types)
+
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index d9a370c1de2..593c7591fc8 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -98,6 +98,7 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
+ 'xlnx-cfi-if.c',
))
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
--
2.34.1
next prev parent reply other threads:[~2023-09-08 17:08 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 17:05 [PULL 00/26] target-arm queue Peter Maydell
2023-09-08 17:05 ` [PULL 01/26] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC Peter Maydell
2023-09-08 17:05 ` [PULL 02/26] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
2023-09-08 17:05 ` [PULL 03/26] target/arm: Add feature detection for FEAT_Pauth2 and extensions Peter Maydell
2023-09-08 17:05 ` [PULL 04/26] target/arm: Don't change pauth features when changing algorithm Peter Maydell
2023-09-08 17:05 ` [PULL 05/26] target/arm: Implement FEAT_PACQARMA3 Peter Maydell
2023-09-08 17:05 ` [PULL 06/26] target/arm: Implement FEAT_EPAC Peter Maydell
2023-09-08 17:05 ` [PULL 07/26] target/arm: Implement FEAT_Pauth2 Peter Maydell
2023-09-08 17:05 ` [PULL 08/26] target/arm: Inform helpers whether a PAC instruction is 'combined' Peter Maydell
2023-09-08 17:05 ` [PULL 09/26] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE Peter Maydell
2023-09-08 17:05 ` [PULL 10/26] hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte() Peter Maydell
2023-09-08 17:05 ` Peter Maydell [this message]
2023-09-08 17:05 ` [PULL 12/26] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Peter Maydell
2023-09-08 17:05 ` [PULL 13/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Peter Maydell
2023-09-08 17:05 ` [PULL 14/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Peter Maydell
2023-09-08 17:05 ` [PULL 15/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Peter Maydell
2023-09-08 17:05 ` [PULL 16/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Peter Maydell
2023-09-08 17:05 ` [PULL 17/26] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR Peter Maydell
2023-09-08 17:05 ` [PULL 18/26] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Peter Maydell
2023-09-08 17:05 ` [PULL 19/26] target/arm: Do not use gen_mte_checkN in trans_STGP Peter Maydell
2023-09-08 17:05 ` [PULL 20/26] arm64: Restore trapless ptimer access Peter Maydell
2023-09-08 17:05 ` [PULL 21/26] target/arm: Implement RMR_ELx Peter Maydell
2023-09-08 17:05 ` [PULL 22/26] target/arm: Implement cortex-a710 Peter Maydell
2023-09-08 17:05 ` [PULL 23/26] target/arm: Implement HCR_EL2.TIDCP Peter Maydell
2023-09-08 17:05 ` [PULL 24/26] target/arm: Implement FEAT_TIDCP1 Peter Maydell
2023-09-08 17:05 ` [PULL 25/26] target/arm: Enable SCTLR_EL1.TIDCP for user-only Peter Maydell
2023-09-08 17:05 ` [PULL 26/26] arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE Peter Maydell
2023-09-11 15:19 ` [PULL 00/26] target-arm queue Stefan Hajnoczi
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