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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/26] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
Date: Fri,  8 Sep 2023 18:05:48 +0100	[thread overview]
Message-ID: <20230908170557.773048-18-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230908170557.773048-1-peter.maydell@linaro.org>

From: Francisco Iglesias <francisco.iglesias@amd.com>

Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-8-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 16 ++++++++++++++
 hw/arm/xlnx-versal.c         | 42 ++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 39ee31185c3..29b9c603010 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -32,6 +32,7 @@
 #include "hw/misc/xlnx-versal-crl.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
 #include "hw/net/xlnx-versal-canfd.h"
+#include "hw/misc/xlnx-versal-cfu.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -117,6 +118,9 @@ struct Versal {
         XlnxEFuse efuse;
         XlnxVersalEFuseCtrl efuse_ctrl;
         XlnxVersalEFuseCache efuse_cache;
+        XlnxVersalCFUAPB cfu_apb;
+        XlnxVersalCFUFDRO cfu_fdro;
+        XlnxVersalCFUSFR cfu_sfr;
 
         OrIRQState apb_irq_orgate;
     } pmc;
@@ -147,6 +151,7 @@ struct Versal {
 #define VERSAL_GEM1_WAKE_IRQ_0     59
 #define VERSAL_ADMA_IRQ_0          60
 #define VERSAL_XRAM_IRQ_0          79
+#define VERSAL_CFU_IRQ_0           120
 #define VERSAL_PMC_APB_IRQ         121
 #define VERSAL_OSPI_IRQ            124
 #define VERSAL_SD0_IRQ_0           126
@@ -240,6 +245,17 @@ struct Versal {
 #define MM_PMC_EFUSE_CACHE          0xf1250000
 #define MM_PMC_EFUSE_CACHE_SIZE     0x00C00
 
+#define MM_PMC_CFU_APB              0xf12b0000
+#define MM_PMC_CFU_APB_SIZE         0x10000
+#define MM_PMC_CFU_STREAM           0xf12c0000
+#define MM_PMC_CFU_STREAM_SIZE      0x1000
+#define MM_PMC_CFU_SFR              0xf12c1000
+#define MM_PMC_CFU_SFR_SIZE         0x1000
+#define MM_PMC_CFU_FDRO             0xf12c2000
+#define MM_PMC_CFU_FDRO_SIZE        0x1000
+#define MM_PMC_CFU_STREAM_2         0xf1f80000
+#define MM_PMC_CFU_STREAM_2_SIZE    0x40000
+
 #define MM_PMC_CRP                  0xf1260000U
 #define MM_PMC_CRP_SIZE             0x10000
 #define MM_PMC_RTC                  0xf12a0000
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 60bf5fe657f..3f4b4b15600 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -570,6 +570,47 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
     qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
 }
 
+static void versal_create_cfu(Versal *s, qemu_irq *pic)
+{
+    SysBusDevice *sbd;
+
+    /* CFU FDRO */
+    object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro,
+                            TYPE_XLNX_VERSAL_CFU_FDRO);
+    sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro);
+
+    sysbus_realize(sbd, &error_fatal);
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO,
+                                sysbus_mmio_get_region(sbd, 0));
+
+    /* CFU APB */
+    object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb,
+                            TYPE_XLNX_VERSAL_CFU_APB);
+    sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb);
+
+    sysbus_realize(sbd, &error_fatal);
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB,
+                                sysbus_mmio_get_region(sbd, 0));
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM,
+                                sysbus_mmio_get_region(sbd, 1));
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2,
+                                sysbus_mmio_get_region(sbd, 2));
+    sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]);
+
+    /* CFU SFR */
+    object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr,
+                            TYPE_XLNX_VERSAL_CFU_SFR);
+
+    sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr);
+
+    object_property_set_link(OBJECT(&s->pmc.cfu_sfr),
+                            "cfu", OBJECT(&s->pmc.cfu_apb), &error_abort);
+
+    sysbus_realize(sbd, &error_fatal);
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR,
+                                sysbus_mmio_get_region(sbd, 0));
+}
+
 static void versal_create_crl(Versal *s, qemu_irq *pic)
 {
     SysBusDevice *sbd;
@@ -763,6 +804,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_pmc_iou_slcr(s, pic);
     versal_create_ospi(s, pic);
     versal_create_crl(s, pic);
+    versal_create_cfu(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.34.1



  parent reply	other threads:[~2023-09-08 17:08 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-08 17:05 [PULL 00/26] target-arm queue Peter Maydell
2023-09-08 17:05 ` [PULL 01/26] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC Peter Maydell
2023-09-08 17:05 ` [PULL 02/26] target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell
2023-09-08 17:05 ` [PULL 03/26] target/arm: Add feature detection for FEAT_Pauth2 and extensions Peter Maydell
2023-09-08 17:05 ` [PULL 04/26] target/arm: Don't change pauth features when changing algorithm Peter Maydell
2023-09-08 17:05 ` [PULL 05/26] target/arm: Implement FEAT_PACQARMA3 Peter Maydell
2023-09-08 17:05 ` [PULL 06/26] target/arm: Implement FEAT_EPAC Peter Maydell
2023-09-08 17:05 ` [PULL 07/26] target/arm: Implement FEAT_Pauth2 Peter Maydell
2023-09-08 17:05 ` [PULL 08/26] target/arm: Inform helpers whether a PAC instruction is 'combined' Peter Maydell
2023-09-08 17:05 ` [PULL 09/26] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE Peter Maydell
2023-09-08 17:05 ` [PULL 10/26] hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte() Peter Maydell
2023-09-08 17:05 ` [PULL 11/26] hw/misc: Introduce the Xilinx CFI interface Peter Maydell
2023-09-08 17:05 ` [PULL 12/26] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Peter Maydell
2023-09-08 17:05 ` [PULL 13/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Peter Maydell
2023-09-08 17:05 ` [PULL 14/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Peter Maydell
2023-09-08 17:05 ` [PULL 15/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Peter Maydell
2023-09-08 17:05 ` [PULL 16/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Peter Maydell
2023-09-08 17:05 ` Peter Maydell [this message]
2023-09-08 17:05 ` [PULL 18/26] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Peter Maydell
2023-09-08 17:05 ` [PULL 19/26] target/arm: Do not use gen_mte_checkN in trans_STGP Peter Maydell
2023-09-08 17:05 ` [PULL 20/26] arm64: Restore trapless ptimer access Peter Maydell
2023-09-08 17:05 ` [PULL 21/26] target/arm: Implement RMR_ELx Peter Maydell
2023-09-08 17:05 ` [PULL 22/26] target/arm: Implement cortex-a710 Peter Maydell
2023-09-08 17:05 ` [PULL 23/26] target/arm: Implement HCR_EL2.TIDCP Peter Maydell
2023-09-08 17:05 ` [PULL 24/26] target/arm: Implement FEAT_TIDCP1 Peter Maydell
2023-09-08 17:05 ` [PULL 25/26] target/arm: Enable SCTLR_EL1.TIDCP for user-only Peter Maydell
2023-09-08 17:05 ` [PULL 26/26] arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE Peter Maydell
2023-09-11 15:19 ` [PULL 00/26] target-arm queue Stefan Hajnoczi

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