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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id b4-20020a05600003c400b0030fd03e3d25sm2200099wrg.75.2023.09.11.00.09.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 00:09:45 -0700 (PDT) Date: Mon, 11 Sep 2023 09:09:44 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org Subject: Re: [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Message-ID: <20230911-da5a16e76fb2dc4fb8df685e@orel> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> <20230906091647.1667171-10-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230906091647.1667171-10-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Sep 06, 2023 at 06:16:36AM -0300, Daniel Henrique Barboza wrote: > This function is used for both accelerators. Make it public, and call it > from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to > split KVM specific code for the KVM accelerator class in the next patch. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 5 ++--- > target/riscv/cpu.h | 1 + > target/riscv/kvm.c | 1 + > 3 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0dc9b3201d..50be127f36 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > satp_map->init |= 1 << satp; > } > > -static void riscv_add_satp_mode_properties(Object *obj) > +void riscv_add_satp_mode_properties(Object *obj) > { > RISCVCPU *cpu = RISCV_CPU(obj); > > @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj, > static void riscv_cpu_add_user_properties(Object *obj) > { > #ifndef CONFIG_USER_ONLY > - riscv_add_satp_mode_properties(obj); > - > if (kvm_enabled()) { > kvm_riscv_cpu_add_kvm_properties(obj); > return; > } > + riscv_add_satp_mode_properties(obj); > #endif > > riscv_cpu_add_misa_properties(obj); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b9c4bea3f7..950c2301f2 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > extern Property riscv_cpu_options[]; > > void riscv_cpu_add_misa_properties(Object *cpu_obj); > +void riscv_add_satp_mode_properties(Object *obj); > > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 7dac01374f..ef6b2cfffe 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -1279,6 +1279,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) > DeviceState *dev = DEVICE(obj); > > riscv_init_user_properties(obj); > + riscv_add_satp_mode_properties(obj); > riscv_cpu_add_misa_properties(obj); > > riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > -- > 2.41.0 > Reviewed-by: Andrew Jones