From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org, "Michael Tsirkin" <mst@redhat.com>,
"Fan Ni" <fan.ni@samsung.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
linux-cxl@vger.kernel.org
Cc: <linuxarm@huawei.com>
Subject: [PATCH v3 2/4] hw/cxl: Add utility functions decoder interleave ways and target count.
Date: Mon, 11 Sep 2023 12:43:11 +0100 [thread overview]
Message-ID: <20230911114313.6144-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230911114313.6144-1-Jonathan.Cameron@huawei.com>
As an encoded version of these key configuration parameters is available
in a register, provide functions to extract it again so as to avoid
the need for duplicating the storage.
Whilst here update the _enc() function to include additional values
as defined in the CXL 3.0 specification. Whilst they are not
currently used in the emulation, they may be in future and it is
easier to compare with the specification if all values are covered.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v3: No changes, picked up tags.
v2: Thanks to Philippe Mathieu-Daudé
- Expand both enc() and dec() functions to include full set of values
defined in CXL r3.0
- Pushed implementation down into the .c file.
---
include/hw/cxl/cxl_component.h | 2 ++
hw/cxl/cxl-component-utils.c | 59 ++++++++++++++++++++++++++++++----
2 files changed, 55 insertions(+), 6 deletions(-)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index bdb3881a6b..ef9e033919 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -226,8 +226,10 @@ void cxl_component_create_dvsec(CXLComponentState *cxl_cstate,
uint16_t type, uint8_t rev, uint8_t *body);
int cxl_decoder_count_enc(int count);
+int cxl_decoder_count_dec(int enc_cnt);
uint8_t cxl_interleave_ways_enc(int iw, Error **errp);
+int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp);
uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp);
hwaddr cxl_decode_ig(int ig);
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index ea2d4770ec..352d0dace2 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -13,15 +13,45 @@
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"
+/* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */
int cxl_decoder_count_enc(int count)
{
switch (count) {
- case 1: return 0;
- case 2: return 1;
- case 4: return 2;
- case 6: return 3;
- case 8: return 4;
- case 10: return 5;
+ case 1: return 0x0;
+ case 2: return 0x1;
+ case 4: return 0x2;
+ case 6: return 0x3;
+ case 8: return 0x4;
+ case 10: return 0x5;
+ /* Switches and Host Bridges may have more than 10 decoders */
+ case 12: return 0x6;
+ case 14: return 0x7;
+ case 16: return 0x8;
+ case 20: return 0x9;
+ case 24: return 0xa;
+ case 28: return 0xb;
+ case 32: return 0xc;
+ }
+ return 0;
+}
+
+int cxl_decoder_count_dec(int enc_cnt)
+{
+ switch (enc_cnt) {
+ case 0x0: return 1;
+ case 0x1: return 2;
+ case 0x2: return 4;
+ case 0x3: return 6;
+ case 0x4: return 8;
+ case 0x5: return 10;
+ /* Switches and Host Bridges may have more than 10 decoders */
+ case 0x6: return 12;
+ case 0x7: return 14;
+ case 0x8: return 16;
+ case 0x9: return 20;
+ case 0xa: return 24;
+ case 0xb: return 28;
+ case 0xc: return 32;
}
return 0;
}
@@ -410,6 +440,23 @@ uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
}
}
+int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp)
+{
+ switch (iw_enc) {
+ case 0x0: return 1;
+ case 0x1: return 2;
+ case 0x2: return 4;
+ case 0x3: return 8;
+ case 0x4: return 16;
+ case 0x8: return 3;
+ case 0x9: return 6;
+ case 0xa: return 12;
+ default:
+ error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc);
+ return 0;
+ }
+}
+
uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
{
switch (gran) {
--
2.39.2
next prev parent reply other threads:[~2023-09-11 11:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-11 11:43 [PATCH v3 0/4] hw/cxl: Support emulating 4 HDM decoders throughout topology Jonathan Cameron via
2023-09-11 11:43 ` [PATCH v3 1/4] hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c Jonathan Cameron via
[not found] ` <CGME20230912161441uscas1p11618b32cdd50462c8267f12e1518e590@uscas1p1.samsung.com>
2023-09-12 16:14 ` Fan Ni
2023-09-11 11:43 ` Jonathan Cameron via [this message]
[not found] ` <CGME20230912172006uscas1p1f48a880aeaf7fad3400929d4bc919ae5@uscas1p1.samsung.com>
2023-09-12 17:20 ` [PATCH v3 2/4] hw/cxl: Add utility functions decoder interleave ways and target count Fan Ni
2023-09-13 8:58 ` Jonathan Cameron via
2023-09-11 11:43 ` [PATCH v3 3/4] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere Jonathan Cameron via
[not found] ` <CGME20230912174357uscas1p23b767b0b88830d2b8a7179439d224a9e@uscas1p2.samsung.com>
2023-09-12 17:43 ` Fan Ni
2023-09-13 6:53 ` Philippe Mathieu-Daudé
2023-09-13 9:01 ` Jonathan Cameron via
2023-09-11 11:43 ` [PATCH v3 4/4] hw/cxl: Support 4 HDM decoders at all levels of topology Jonathan Cameron via
[not found] ` <CGME20230912180845uscas1p28e989eaff6b92939cfdb85886137354b@uscas1p2.samsung.com>
2023-09-12 18:08 ` Fan Ni
2023-09-13 9:03 ` Jonathan Cameron via
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