Re: [PATCH v2 3/3] hw/cxl: Support 4 HDM decoders at all levels of topology

[Jonathan Cameron via <qemu-devel@nongnu.org>]

On Thu, 7 Sep 2023 14:41:16 +0200
Philippe Mathieu-Daudé <philmd@linaro.org> wrote:

> On 7/9/23 13:35, Jonathan Cameron wrote:
> > Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
> > and CXL Type 3 end points.
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >   include/hw/cxl/cxl_component.h |  10 ++++
> >   hw/cxl/cxl-component-utils.c   |  27 +++++----
> >   hw/cxl/cxl-host.c              |  65 ++++++++++++++-------
> >   hw/mem/cxl_type3.c             | 100 +++++++++++++++++++++++----------
> >   4 files changed, 140 insertions(+), 62 deletions(-)  
> 
> If you ever have to respin, please split the 'hdm_inc' introduction
> in a preliminary patch, to reduce the number of changes and the
> probability of missing a bug.
> 

I didn't do this originally because it's a bit interleaved with the
other changes.  I can make this separable by adding the register definitions
for HDM decoder 1 and a note that it's only used for offset calcs.

I've also pushed it into various other functions that before the
other changes in here don't attempt to deal with multiple hdm decoders
at all.

Didn't end up looking too bad.

Whilst changing this, I noticed a bug where in one place the encoded version
of the hdm count was being used undecoded. So all good in the end :)

Jonathan