* [PATCH 00/10] TriCore tests and cleanups
@ 2023-09-13 10:53 Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 01/10] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Hi,
this series adds a test for many of the arithmetic instructions of the TriCore.
The goal here is that each TriCore instruction is eventually at least run once in CI.
While at this, I also cleaned up cpu.h, which contained a copy of the core special
function registers (CSFR). These are already defined in csfr.h.inc, so I use
this definition.
I also changed the types of the effective address (ea) in op_helper.c to
target_ulong, as it cannot be sign extened.
Cheers,
Bastian
Bastian Koppelmann (10):
tests/tcg/tricore: Extended and non-extened regs now match
hw/tricore: Log failing test in testdevice
tests/tcg: Reset result register after each test
tests/tcg/tricore: Add test for all arith insns up to addx
tests/tcg/tricore: Add test for and to csub
tests/tcg/tricore: Add from dextr to lt
tests/tcg/tricore: Add test from 'max' to 'shas'
tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
target/tricore: Remove CSFRs from cpu.h
target/tricore: Change effective address (ea) to target_ulong
hw/tricore/tricore_testdevice.c | 4 +
target/tricore/cpu.h | 143 +----------
target/tricore/op_helper.c | 16 +-
tests/tcg/tricore/Makefile.softmmu-target | 3 +-
tests/tcg/tricore/asm/macros.h | 166 +++++++++++--
tests/tcg/tricore/asm/test_arith.S | 280 ++++++++++++++++++++++
6 files changed, 447 insertions(+), 165 deletions(-)
create mode 100644 tests/tcg/tricore/asm/test_arith.S
--
2.42.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 01/10] tests/tcg/tricore: Extended and non-extened regs now match
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 02/10] hw/tricore: Log failing test in testdevice Bastian Koppelmann
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 38 +++++++++++++++++-----------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 17e696bef5..0f349dbf1e 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -12,31 +12,31 @@
#define TESTDEV_ADDR 0xf0000000
/* Register definitions */
#define DREG_RS1 %d0
-#define DREG_RS2 %d1
-#define DREG_RS3 %d2
-#define DREG_CALC_RESULT %d3
-#define DREG_CALC_PSW %d4
-#define DREG_CORRECT_PSW %d5
-#define DREG_TEMP_LI %d10
-#define DREG_TEMP %d11
-#define DREG_TEST_NUM %d14
-#define DREG_CORRECT_RESULT %d15
-#define DREG_CORRECT_RESULT_2 %d13
+#define DREG_RS2 %d2
+#define DREG_RS3 %d4
+#define DREG_CALC_RESULT %d5
+#define DREG_CALC_PSW %d6
+#define DREG_CORRECT_PSW %d7
+#define DREG_TEMP_LI %d13
+#define DREG_TEMP %d14
+#define DREG_TEST_NUM %d8
+#define DREG_CORRECT_RESULT %d9
+#define DREG_CORRECT_RESULT_2 %d10
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
#define DREG_DEV_ADDR %a15
-#define EREG_RS1 %e6
-#define EREG_RS1_LO %d6
-#define EREG_RS1_HI %d7
-#define EREG_RS2 %e8
-#define EREG_RS2_LO %d8
-#define EREG_RS2_HI %d9
-#define EREG_CALC_RESULT %e8
-#define EREG_CALC_RESULT_HI %d9
-#define EREG_CALC_RESULT_LO %d8
+#define EREG_RS1 %e0
+#define EREG_RS1_LO %d0
+#define EREG_RS1_HI %d1
+#define EREG_RS2 %e2
+#define EREG_RS2_LO %d2
+#define EREG_RS2_HI %d3
+#define EREG_CALC_RESULT %e6
+#define EREG_CALC_RESULT_LO %d6
+#define EREG_CALC_RESULT_HI %d7
#define EREG_CORRECT_RESULT_LO %d0
#define EREG_CORRECT_RESULT_HI %d1
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 02/10] hw/tricore: Log failing test in testdevice
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 01/10] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 03/10] tests/tcg: Reset result register after each test Bastian Koppelmann
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
hw/tricore/tricore_testdevice.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..d0f8db9089 100644
--- a/hw/tricore/tricore_testdevice.c
+++ b/hw/tricore/tricore_testdevice.c
@@ -16,6 +16,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "hw/tricore/tricore_testdevice.h"
@@ -23,6 +24,9 @@
static void tricore_testdevice_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
+ if (value != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Test %ld failed!\n", value);
+ }
exit(value);
}
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 03/10] tests/tcg: Reset result register after each test
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 01/10] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 02/10] hw/tricore: Log failing test in testdevice Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 04/10] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 0f349dbf1e..e831f73721 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -46,7 +46,8 @@ test_ ## num: \
code; \
LI(DREG_CORRECT_RESULT, correct) \
mov DREG_TEST_NUM, num; \
- jne testreg, DREG_CORRECT_RESULT, fail \
+ jne testreg, DREG_CORRECT_RESULT, fail; \
+ mov testreg, 0
#define TEST_CASE_E(num, correct_lo, correct_hi, code...) \
test_ ## num: \
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 04/10] tests/tcg/tricore: Add test for all arith insns up to addx
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (2 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 03/10] tests/tcg: Reset result register after each test Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 05/10] tests/tcg/tricore: Add test for and to csub Bastian Koppelmann
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 3 +-
tests/tcg/tricore/asm/macros.h | 50 +++++++++++++++++++++++
tests/tcg/tricore/asm/test_arith.S | 41 +++++++++++++++++++
3 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/tricore/asm/test_arith.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index afcf41a977..018858c592 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -6,6 +6,7 @@ LDFLAGS = -T$(TESTS_PATH)/link.ld --mcpu=tc162
ASFLAGS = -mtc162
CFLAGS = -mtc162 -c -I$(TESTS_PATH)
+TESTS += test_arith.asm.tst
TESTS += test_abs.asm.tst
TESTS += test_bmerge.asm.tst
TESTS += test_clz.asm.tst
@@ -29,7 +30,7 @@ TESTS += test_muls.asm.tst
TESTS += test_boot_to_main.c.tst
TESTS += test_context_save_areas.c.tst
-QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
+QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -d guest_errors -kernel
%.pS: $(ASM_TESTS_PATH)/%.S
$(HOST_CC) -E -o $@ $<
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index e831f73721..8ed2249b0d 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -112,6 +112,11 @@ test_ ## num: \
insn DREG_CORRECT_RESULT, DREG_RS1; \
)
+#define TEST_D_I(insn, num, result, imm) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ insn DREG_CALC_RESULT, imm; \
+ )
+
#define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
@@ -129,6 +134,51 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2; \
)
+#define TEST_D_DI(insn, num, result, rs1, imm1) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1; \
+ )
+
+#define TEST_D_D15I(insn, num, result, rs1, imm1) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(%d15, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, %d15, imm1; \
+ )
+
+#define TEST_D15_DD(insn, num, result, rs1, rs2) \
+ TEST_CASE(num, %d15, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn %d15, DREG_RS1, DREG_RS2; \
+ )
+
+#define TEST_D15_DI(insn, num, result, rs1, imm) \
+ TEST_CASE(num, %d15, result, \
+ LI(DREG_RS1, rs1); \
+ rstv; \
+ insn %d15, DREG_RS1, imm; \
+ )
+
+#define TEST_D_DD(insn, num, result, rs1, rs2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2; \
+ )
+
+#define TEST_D_D15D(insn, num, result, rs1, rs2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(%d15, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, %d15, DREG_RS2; \
+ )
+
#define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
new file mode 100644
index 0000000000..07c4b876e9
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -0,0 +1,41 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(abs, 1, 0x778636a7, 0x778636a7 )
+ TEST_D_D(abs.b, 2, 0x497a4902, 0xb786b702 )
+ TEST_D_D(abs.h, 3, 0x48331698, 0xb7cde968 )
+ TEST_D_DI(absdif, 4, 0x22a52402, 0xdd5adc1a ,0x1c )
+ TEST_D_DD(absdif, 5, 0x1e106273, 0x56f0cea3 ,0x75013116 )
+ TEST_D_DD(absdif.b, 6, 0xa650a3b, 0xa7ee8b2a ,0x9d899565 )
+ TEST_D_DD(absdif.h, 7, 0x7dd06888, 0x88292922 ,0x5f9c09a )
+ TEST_D_DI(absdifs, 8, 0x79adddf7, 0x865222d1 ,0xc8 )
+ TEST_D_DD(absdifs, 9, 0x7fffffff, 0x2ac1008b ,0x80032055 )
+ TEST_D_DD(absdifs.h, 10, 0x65ae7fff, 0xf70a7a05 ,0x915cc1b3 )
+ TEST_D_D(abss, 11, 0x2a671868, 0xd598e798 )
+ TEST_D_D(abss.h, 12, 0x60fc7ce5, 0x9f04831b )
+ TEST_D_DI(add, 13, 0x951ce738, 0x951ce6b4 ,0x84 )
+ TEST_D_DD(add, 14, 0x53975df5, 0xc003e25a ,0x93937b9b )
+ TEST_D_I(add, 15, 0x5, 0x5 )
+ TEST_D_D15I(add, 16, 0x3c330214, 0x3c33020f ,0x5 )
+ TEST_D15_DI(add, 17, 0x55eb1b8, 0x55eb1b8 ,0x0 )
+ TEST_D_D(add, 18, 0xe66ead54, 0xe66ead54 )
+ TEST_D_D15D(add, 19, 0xe450f787, 0xc7100fee ,0x1d40e799 )
+ TEST_D15_DD(add, 20, 0x73f6d886, 0x27ca8a80 ,0x4c2c4e06 )
+ TEST_D_DD(add.b, 21, 0x631bd462, 0xf9702965 ,0x6aababfd )
+ TEST_D_DD(add.h, 22, 0x76ce127a, 0xf5402796 ,0x818eeae4 )
+ TEST_D_DI(addc, 23, 0xcf8399c3, 0xcf839920 ,0xa3 )
+ TEST_D_DD(addc, 24, 0xa455054c, 0x85d0b9ed ,0x1e844b5f )
+ TEST_D_DI(addi, 25, 0xbf202fe6, 0xbf1fd903 ,0x56e3 )
+ TEST_D_DI(addih, 26, 0xf28a99cc, 0xc10499cc ,12678 )
+ TEST_D_DI(adds, 27, 0x233892ad, 0x233892ad ,0x0 )
+ TEST_D_DD(adds, 28, 0xc1b1184d, 0x100a2339 ,0xb1a6f514 )
+ TEST_D_D(adds, 29, 0x19143e9a, 0x19143e9a )
+ TEST_D_DD(adds.h, 30, 0x7fff9de3, 0x668ebcc8 ,0x7462e11b )
+ TEST_D_DD(adds.hu, 31, 0xffffffff, 0xbe0776eb ,0x5d69b388 )
+ TEST_D_DI(adds.u, 32, 0x84c176ba, 0x84c176a9 ,0x11 )
+ TEST_D_DD(adds.u, 33, 0xffffffff, 0xd4a91e39 ,0x55b1baed )
+ TEST_D_DI(addx, 34, 0x38f63b5, 0x38f632b ,0x8a )
+ TEST_D_DD(addx, 35, 0x8b9da5a4, 0x16e32e7 ,0x8a2f72bd )
+
+ TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 05/10] tests/tcg/tricore: Add test for and to csub
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (3 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 04/10] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 06/10] tests/tcg/tricore: Add from dextr to lt Bastian Koppelmann
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 11 +++++++
tests/tcg/tricore/asm/test_arith.S | 47 ++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 8ed2249b0d..3000e15590 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -117,6 +117,11 @@ test_ ## num: \
insn DREG_CALC_RESULT, imm; \
)
+#define TEST_D15_I(insn, num, result, imm) \
+ TEST_CASE(num, %d15, result, \
+ insn %d15, imm; \
+ )
+
#define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
@@ -236,6 +241,12 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
)
+#define TEST_E_D(insn, num, res_lo, res_hi, rs1) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ insn EREG_CALC_RESULT, DREG_RS1; \
+ )
+
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index 07c4b876e9..ec87413777 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -37,5 +37,52 @@ _start:
TEST_D_DD(adds.u, 33, 0xffffffff, 0xd4a91e39 ,0x55b1baed )
TEST_D_DI(addx, 34, 0x38f63b5, 0x38f632b ,0x8a )
TEST_D_DD(addx, 35, 0x8b9da5a4, 0x16e32e7 ,0x8a2f72bd )
+ TEST_D_DI(and, 36, 0x1, 0xf9683907 ,0x69 )
+ TEST_D_DD(and, 37, 0x40102090, 0x48d86c91 ,0x511123d0 )
+ TEST_D15_I(and, 38, 0x0, 0x1a )
+ TEST_D_D(and, 39, 0x0, 0x551343d6 )
+ TEST_D_DIDI(and.and.t, 40, 0x0, 0x60343d14 ,0x4 ,0x922020d8 ,0x3 )
+ TEST_D_DIDI(and.andn.t, 41, 0x0, 0xd4f95dad ,0x5 ,0xb9fff576 ,0x3 )
+ TEST_D_DI(and.eq, 42, 0x0, 0x9945aaf ,0xf )
+ TEST_D_DD(and.eq, 43, 0x0, 0x32a94b38 ,0xf53b9463 )
+ TEST_D_DI(and.ge, 44, 0x0, 0xe66d0f6e ,0x55 )
+ TEST_D_DD(and.ge, 45, 0x0, 0x43ea87d0 ,0x5adacf4d )
+ TEST_D_DI(and.ge.u, 46, 0x0, 0x4bef5bd1 ,0xb3 )
+ TEST_D_DD(and.ge.u, 47, 0x0, 0x9b5504c2 ,0x3787f19 )
+ TEST_D_DI(and.lt, 48, 0x0, 0x36daf216 ,0xc8 )
+ TEST_D_DD(and.lt, 49, 0x0, 0x6bf175f7 ,0x769bc7db )
+ TEST_D_DI(and.lt.u, 50, 0x0, 0xbef4b04a ,0x1d )
+ TEST_D_DD(and.lt.u, 51, 0x0, 0xa89ea455 ,0x84dc9898 )
+ TEST_D_DI(and.ne, 52, 0x0, 0xf3bb3559 ,0x5e )
+ TEST_D_DD(and.ne, 53, 0x0, 0xa05258eb ,0x50c5b0e4 )
+ TEST_D_DIDI(and.nor.t, 54, 0x0, 0xd7534767 ,0x1 ,0x5fac529f ,0x6 )
+ TEST_D_DIDI(and.or.t, 55, 0x0, 0xa3dd1690 ,0x7 ,0xe25f7361 ,0x4 )
+ TEST_D_DIDI(and.t, 56, 0x0, 0x9f6f71d5 ,0x1 ,0xe9dfe144 ,0x2 )
+ TEST_D_DI(andn, 57, 0xb2ed0c01, 0xb2ed0cf1 ,0xfc )
+ TEST_D_DD(andn, 58, 0x102d884, 0x494ad98c ,0xf87d077a )
+ TEST_D_DIDI(andn.t, 59, 0x0, 0x24ef957a ,0x5 ,0xaf95e01e ,0x4 )
+ TEST_D_DD(bmerge, 60, 0xbfe56f84, 0x2a0fc78 ,0xf7127bb2 )
+ TEST_E_D(bsplit, 61, 0x1ae2, 0xef60, 0xa9ee7c04 )
+ TEST_D_DDI(cadd, 62, 0x3ac01dec, 0x7770d9a ,0x3ac01d3d ,0xaf )
+ TEST_D_DDD(cadd, 63, 0x48a771b4, 0xdf020dda ,0xb81cdead ,0x908a9307 )
+ TEST_D_D15I(cadd, 64, 0x4, 0x6a766c11 ,0x4 )
+ TEST_D_DDI(caddn, 65, 0xdc0cd85d, 0xfe1fbf45 ,0xdc0cd85d ,0x1c )
+ TEST_D_DDD(caddn, 66, 0xd7bd5cb5, 0x70a930bd ,0xd7bd5cb5 ,0xb5dce80d )
+ TEST_D_D15I(caddn, 67, 0x0, 0xb6051252 ,0x4 )
+ TEST_D_D(clo, 68, 0x1, 0xa15f7ebc )
+ TEST_D_D(clo.h, 69, 0x0, 0x2bf418ef )
+ TEST_D_D(cls, 70, 0x1, 0xcbda5b50 )
+ TEST_D_D(cls.h, 71, 0x10001, 0xd15ac540 )
+ TEST_D_D(clz, 72, 0x1, 0x62ddf743 )
+ TEST_D_D(clz.h, 73, 0x0, 0xa859df54 )
+ TEST_D_D15I(cmov, 74, 0x5, 0x7d06b438 ,0x5 )
+ TEST_D_D15D(cmov, 75, 0x4d24e162, 0xd07651a5 ,0x4d24e162 )
+ TEST_D_D15I(cmovn, 76, 0x0, 0xea576d5 ,0x6 )
+ TEST_D_D15D(cmovn, 77, 0x0, 0x6a1d2b48 ,0xb28bc831 )
+ TEST_D_DD(crc32.b, 78, 0x3baca290, 0xcde828a2 ,0x869b2ea4 )
+ TEST_D_DD(crc32b.w, 79, 0x7f9d8908, 0xdaf396a5 ,0xa9011cf2 )
+ TEST_D_DD(crc32l.w, 80, 0x1707579b, 0x87572060 ,0x8cdfa395 )
+ TEST_D_DDD(csub, 81, 0xf389f12f, 0xae9c7e04 ,0x63247211 ,0x6f9a80e2 )
+ TEST_D_DDD(csubn, 82, 0x2a7dd20d, 0xc39caf46 ,0x2a7dd20d ,0xa8ab6269 )
TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 06/10] tests/tcg/tricore: Add from dextr to lt
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (4 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 05/10] tests/tcg/tricore: Add test for and to csub Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 07/10] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 51 ++++++++++++++++++++++++++--
tests/tcg/tricore/asm/test_arith.S | 53 ++++++++++++++++++++++++++++++
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 3000e15590..92f0f7b22b 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -34,6 +34,9 @@
#define EREG_RS2 %e2
#define EREG_RS2_LO %d2
#define EREG_RS2_HI %d3
+#define EREG_RS3 %e4
+#define EREG_RS3_LO %d4
+#define EREG_RS3_HI %d5
#define EREG_CALC_RESULT %e6
#define EREG_CALC_RESULT_LO %d6
#define EREG_CALC_RESULT_HI %d7
@@ -131,6 +134,26 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
)
+#define TEST_D_DDDI(insn, num, result, rs1, rs2, rs3, imm) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ LI(DREG_RS3, rs3); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3, imm; \
+ )
+
+
+#define TEST_D_DDE(insn, num, result, rs1, rs2, rs3_lo, rs3_hi) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ LI(EREG_RS3_LO, rs3_lo); \
+ LI(EREG_RS3_HI, rs3_hi); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, EREG_RS3; \
+ )
+
#define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
@@ -209,6 +232,12 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
+#define TEST_E_DII(insn, num, res_lo, res_hi, rs1, imm1, imm2) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ insn EREG_CALC_RESULT, DREG_RS1, imm1, imm2; \
+ )
+
#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
@@ -247,7 +276,7 @@ test_ ## num: \
insn EREG_CALC_RESULT, DREG_RS1; \
)
-#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
+#define TEST_E_ED(insn, num, res_lo, res_hi, rs1_lo, rs1_hi, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
LI(EREG_RS1_HI, rs1_hi); \
@@ -255,14 +284,32 @@ test_ ## num: \
insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
)
-#define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \
+#define TEST_E_IDI(insn, num, res_lo, res_hi, imm1, rs1, imm2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(DREG_RS1, rs1); \
rstv; \
insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2; \
)
+#define TEST_E_DD(insn, num, res_lo, res_hi, rs1, rs2) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ insn EREG_CALC_RESULT, DREG_RS1, DREG_RS2; \
+ )
+#define TEST_E_DDI(insn, num, res_lo, res_hi, rs1, rs2, imm) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ insn EREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
+ )
+
+#define TEST_E_III(insn, num, res_lo, res_hi, imm1, imm2, imm3) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ rstv; \
+ insn EREG_CALC_RESULT, imm1, imm2, imm3; \
+ )
/* Pass/Fail handling part */
#define TEST_PASSFAIL \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index ec87413777..68b6715cb9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -84,5 +84,58 @@ _start:
TEST_D_DD(crc32l.w, 80, 0x1707579b, 0x87572060 ,0x8cdfa395 )
TEST_D_DDD(csub, 81, 0xf389f12f, 0xae9c7e04 ,0x63247211 ,0x6f9a80e2 )
TEST_D_DDD(csubn, 82, 0x2a7dd20d, 0xc39caf46 ,0x2a7dd20d ,0xa8ab6269 )
+ TEST_D_DDI(dextr, 83, 0x6b245592, 0x90d648ab ,0x2436a08d ,0x7 )
+ TEST_D_DDD(dextr, 84, 0x4e9d8172, 0x6b8c6274 ,0xec0b9772 ,0x7ab0d8f5 )
+ TEST_E_ED(dvadj, 85, 0xfb793929 ,0xf15f4ecc, 0xfb793928 ,0xf15f4ecc ,0x5de9a7b4 )
+ TEST_E_DD(dvinit, 86, 0xbbd99367 ,0xffffffff, 0xbbd99367 ,0xa248dff9 )
+ TEST_E_DD(dvinit.b, 87, 0x58ffffff ,0x1f3f20, 0x1f3f2058 ,0xfed6c3ec )
+ TEST_E_DD(dvinit.bu, 88, 0xa000000 ,0x8bbf54, 0x8bbf540a ,0xa0bcfdde )
+ TEST_E_DD(dvinit.h, 89, 0xfe59ffff ,0x6d07, 0x6d07fe59 ,0xe4a6e12c )
+ TEST_E_DD(dvinit.hu, 90, 0x8e5d0000 ,0x37bd, 0x37bd8e5d ,0x38c0be4c )
+ TEST_E_DD(dvinit.u, 91, 0x613ca148 ,0x0, 0x613ca148 ,0x79e89e70 )
+ TEST_E_ED(dvstep.u, 92, 0x90388180 ,0x356c3f47, 0x47903881 ,0xd5b131ef ,0xa8f78b60 )
+ TEST_D_DI(eq, 93, 0x0, 0x22cf24bc ,0x3c )
+ TEST_D_DD(eq, 94, 0x0, 0x1b220983 ,0x60d6182 )
+ TEST_D15_DI(eq, 95, 0x0, 0x66b1313e ,0x1 )
+ TEST_D15_DD(eq, 96, 0x0, 0x3a6b6484 ,0xe1bdc794 )
+ TEST_D_DD(eq.b, 97, 0x0, 0x1413e6a2 ,0x8237ab11 )
+ TEST_D_DD(eq.h, 98, 0x0, 0xc2d2cdd3 ,0xfd8576be )
+ TEST_D_DD(eq.w, 99, 0x0, 0x1b6f66d7 ,0x738035d1 )
+ TEST_D_DI(eqany.b, 100, 0x0, 0xfb630c56 ,0x9f )
+ TEST_D_DD(eqany.b, 101, 0x0, 0x5cdbbb44 ,0xf7911917 )
+ TEST_D_DI(eqany.h, 102, 0x0, 0xd31af4d0 ,0xc )
+ TEST_D_DD(eqany.h, 103, 0x0, 0x6bd800e2 ,0x8bea6be7 )
+ TEST_D_DI(ge, 104, 0x1, 0x3d3d0f67 ,0x6d )
+ TEST_D_DD(ge, 105, 0x1, 0x7238ba92 ,0x3d6d3327 )
+ TEST_D_DI(ge.u, 106, 0x1, 0xc34402cb ,0xf2 )
+ TEST_D_DD(ge.u, 107, 0x1, 0xf44ec751 ,0x42f3f12d )
+ TEST_E_III(imask, 108, 0x1c0 ,0x1c0, 0x7 ,0x6 ,0x3 )
+ TEST_E_IDI(imask, 109, 0x1 ,0x7f, 0x1 ,0xa7390380 ,0x7 )
+ TEST_E_DII(imask, 110, 0x3fdaaa80 ,0x1fc0, 0x14ff6aaa ,0x6 ,0x7 )
+ TEST_E_DDI(imask, 111, 0xfc8a94c0 ,0x1f0, 0xafc8a94c ,0x37ceafe4 ,0x5 )
+ TEST_D_DIDI(ins.t, 112, 0x3991c755, 0x3991c755 ,0x2 ,0xa9b171ef ,0x4 )
+ TEST_D_DIII(insert, 113, 0x9997e4d7, 0x9997e497 ,0x6 ,0x5 ,0x2 )
+ TEST_D_DIE(insert, 114, 0x71169ed, 0xaf1169ed ,0x1 ,0xf5abe69a ,0xaef09348 )
+ TEST_D_DIDI(insert, 115, 0x8a228466, 0x8a2284e6 ,0x5 ,0x2c808a7f ,0x2 )
+ TEST_D_DDII(insert, 116, 0xeffef7ec, 0xeffef7e8 ,0xaa92b4ce ,0x1 ,0x3 )
+ TEST_D_DDE(insert, 117, 0x7948cba3, 0x818b7ba3 ,0x70bca465 ,0x47ede909 ,0xbf4f8afe )
+ TEST_D_DDDI(insert, 118, 0x5e974875, 0x5b774875 ,0x27f33374 ,0x4b417135 ,0x7 )
+ TEST_D_DIDI(insn.t, 119, 0xcbbe860a, 0xcbbe860a ,0x4 ,0xd2f483d9 ,0x3 )
+ TEST_E_ED(ixmax, 120, 0x48ef48f1 ,0x6e7e, 0x687e48ef ,0x9afdc6c8 ,0xbd066e7e )
+ TEST_E_ED(ixmax.u, 121, 0xac97ac98 ,0xd968, 0x67b7ac96 ,0x55371874 ,0xd968399e )
+ TEST_E_ED(ixmin, 122, 0x957f9580 ,0xa9de, 0x8ed957e ,0x9519d426 ,0xa9de69e1 )
+ TEST_E_ED(ixmin.u, 123, 0xde48de4a ,0x3660, 0x3dc4de48 ,0x1e5a559d ,0xdbc53660 )
+ TEST_D_DI(lt, 124, 0x1, 0xf156e5c0 ,0x40 )
+ TEST_D_DD(lt, 125, 0x0, 0x51c83765 ,0x1aa7292 )
+ TEST_D15_DI(lt, 126, 0x0, 0x31163fc9 ,0x5 )
+ TEST_D15_DD(lt, 127, 0x1, 0xf9e43e50 ,0x22a3f8d5 )
+ TEST_D_DD(lt.b, 128, 0xff0000, 0x4a374b04 ,0x4869ba92 )
+ TEST_D_DD(lt.bu, 129, 0xff00, 0x4c5bb0c7 ,0x4c3bd2a3 )
+ TEST_D_DD(lt.h, 130, 0xffff0000, 0x326e5bdc ,0x33e03761 )
+ TEST_D_DD(lt.hu, 131, 0x0, 0xf53b8e9b ,0x53cc7810 )
+ TEST_D_DI(lt.u, 132, 0x0, 0xf1f78a54 ,0x4d )
+ TEST_D_DD(lt.u, 133, 0x1, 0x10fedada ,0x265af026 )
+ TEST_D_DD(lt.w, 134, 0xffffffff, 0xbc8a0b22 ,0x3dd6d1a2 )
+ TEST_D_DD(lt.wu, 135, 0x0, 0xcc92a312 ,0x133c8a9d )
TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 07/10] tests/tcg/tricore: Add test from 'max' to 'shas'
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (5 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 06/10] tests/tcg/tricore: Add from dextr to lt Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 08/10] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 13 ++++
tests/tcg/tricore/asm/test_arith.S | 105 +++++++++++++++++++++++++++++
2 files changed, 118 insertions(+)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 92f0f7b22b..5bba9dbbf6 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -143,6 +143,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3, imm; \
)
+#define TEST_D_ED(insn, num, result, rs1_lo, rs1_hi, rs2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(EREG_RS1_LO, rs1_lo); \
+ LI(EREG_RS1_HI, rs1_hi); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
+ )
#define TEST_D_DDE(insn, num, result, rs1, rs2, rs3_lo, rs3_hi) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
@@ -284,6 +292,11 @@ test_ ## num: \
insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
)
+#define TEST_E_I(insn, num, res_lo, res_hi, imm) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ insn EREG_CALC_RESULT, imm; \
+ )
+
#define TEST_E_IDI(insn, num, res_lo, res_hi, imm1, rs1, imm2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index 68b6715cb9..728509cfa9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -137,5 +137,110 @@ _start:
TEST_D_DD(lt.u, 133, 0x1, 0x10fedada ,0x265af026 )
TEST_D_DD(lt.w, 134, 0xffffffff, 0xbc8a0b22 ,0x3dd6d1a2 )
TEST_D_DD(lt.wu, 135, 0x0, 0xcc92a312 ,0x133c8a9d )
+ TEST_D_DI(max, 136, 0xe0d4d31, 0xe0d4d31 ,0x58 )
+ TEST_D_DD(max, 137, 0x787135d1, 0x787135d1 ,0x14c4da7b )
+ TEST_D_DD(max.b, 138, 0x316b2c0f, 0x316bd4cb ,0x2b2c0f )
+ TEST_D_DD(max.bu, 139, 0x5f88a94e, 0x4675a04e ,0x5f88a92b )
+ TEST_D_DD(max.h, 140, 0x532f72fd, 0x532fad08 ,0x4b1272fd )
+ TEST_D_DD(max.hu, 141, 0xeed88225, 0x116b7eea ,0xeed88225 )
+ TEST_D_DI(max.u, 142, 0xf342d496, 0xf342d496 ,0x38 )
+ TEST_D_DD(max.u, 143, 0xdd15066d, 0xdd15066d ,0xf556c66 )
+ TEST_D_DI(min, 144, 0xdd, 0x731a9dec ,0xdd )
+ TEST_D_DD(min, 145, 0x23ed2038, 0x2e3f1040 ,0x23ed2038 )
+ TEST_D_DD(min.b, 146, 0xf1aba6b6, 0x26aba6b6 ,0xf17eb628 )
+ TEST_D_DD(min.bu, 147, 0x3f500949, 0x8a500c52 ,0x3fe70949 )
+ TEST_D_DD(min.h, 148, 0xad296b7, 0xe917617 ,0xad296b7 )
+ TEST_D_DD(min.hu, 149, 0x859351e, 0xc6a351e ,0x8595c29 )
+ TEST_D_DI(min.u, 150, 0x3, 0x8e14bfbf ,0x3 )
+ TEST_D_DD(min.u, 151, 0x371cf628, 0x371cf628 ,0xe837ca8f )
+ TEST_D_I(mov, 152, 0x391, 0x391 )
+ TEST_E_I(mov, 153, 0x4612 ,0x0, 0x4612 )
+ TEST_D_D(mov, 154, 0x57de4d85, 0x57de4d85 )
+ TEST_E_D(mov, 155, 0x81fcfe47 ,0xffffffff, 0x81fcfe47 )
+ TEST_E_DD(mov, 156, 0xa33b7b80 ,0x8a2a74b7, 0x8a2a74b7 ,0xa33b7b80 )
+ TEST_D15_I(mov, 157, 0x3b, 0x3b )
+ TEST_D_I(mov, 158, 0x2, 0x2 )
+ TEST_E_I(mov, 159, 0x1 ,0x0, 0x1 )
+ TEST_D_D(mov, 160, 0x1557688b, 0x1557688b )
+ TEST_D_I(mov.u, 161, 0x502, 0x502 )
+ TEST_D_I(movh, 162, 0x60ea0000, 0x60ea)
+ TEST_D_DI(nand, 163, 0xfffffffe, 0x291af609 ,0xd7 )
+ TEST_D_DD(nand, 164, 0xfaffe4fe, 0x270e5faf ,0xcd613b01 )
+ TEST_D_DIDI(nand.t, 165, 0x1, 0xe10d5151 ,0x1 ,0x84f18d6b ,0x7 )
+ TEST_D_DI(ne, 166, 0x1, 0xed148b6 ,0x66 )
+ TEST_D_DD(ne, 167, 0x1, 0x9b38284a ,0x25948edd )
+ TEST_D_DI(nor, 168, 0x77f45c1a, 0x880ba324 ,0xe5 )
+ TEST_D_DD(nor, 169, 0x2c8103c0, 0x93382c3f ,0x5266d42b )
+ TEST_D_DIDI(nor.t, 170, 0x1, 0x3f964a10 ,0x7 ,0x54e26b8e ,0x3 )
+ TEST_D_DI(or, 171, 0xbf29afdf, 0xbf29afd3 ,0x4e )
+ TEST_D_DD(or, 172, 0xfbefe7cf, 0x2a896747 ,0xdb66a2ce )
+ TEST_D15_I(or, 173, 0xb, 0xb )
+ TEST_D_D(or, 174, 0x3ef404a0, 0x3ef404a0 )
+ TEST_D_DIDI(or.and.t, 175, 0x1, 0x1e09424a ,0x3 ,0xe427b416 ,0x3 )
+ TEST_D_DIDI(or.andn.t, 176, 0x0, 0x4a560efb ,0x1 ,0xf0596f84 ,0x3 )
+ TEST_D_DI(or.eq, 177, 0x0, 0xee8c7017 ,0xcf )
+ TEST_D_DD(or.eq, 178, 0x0, 0xc33e8cf0 ,0x139c3f75 )
+ TEST_D_DI(or.ge, 179, 0x1, 0x4845ad04 ,0xf1 )
+ TEST_D_DD(or.ge, 180, 0x1, 0x687040a1 ,0xf61bdd8c )
+ TEST_D_DI(or.ge.u, 181, 0x1, 0x55edca06 ,0xa1 )
+ TEST_D_DD(or.ge.u, 182, 0x0, 0x8c975e46 ,0xd26c95ea )
+ TEST_D_DI(or.lt, 183, 0x1, 0xbcb87506 ,0x43 )
+ TEST_D_DD(or.lt, 184, 0x0, 0x2c9ea431 ,0x1d1515 )
+ TEST_D_DI(or.lt.u, 185, 0x0, 0x7bbfdf3b ,0xe7 )
+ TEST_D_DD(or.lt.u, 186, 0x1, 0x2f71485e ,0xe9219409 )
+ TEST_D_DI(or.ne, 187, 0x1, 0xc9b87ffc ,0x65 )
+ TEST_D_DD(or.ne, 188, 0x1, 0xd5746862 ,0x72d5cbc1 )
+ TEST_D_DIDI(or.nor.t, 189, 0x0, 0xa0d6cc1 ,0x7 ,0x38e6fc83 ,0x1 )
+ TEST_D_DIDI(or.or.t, 190, 0x1, 0x85546ea7 ,0x4 ,0xffd58bc6 ,0x2 )
+ TEST_D_DIDI(or.t, 191, 0x0, 0xd594ef27 ,0x3 ,0xdb878237 ,0x4 )
+ TEST_D_DI(orn, 192, 0xffffffdf, 0xc8b4cb5d ,0x64 )
+ TEST_D_DD(orn, 193, 0xf2ffd5eb, 0xe2ef556a ,0xaf6d3a3e )
+ TEST_D_DIDI(orn.t, 194, 0x1, 0xb511c09 ,0x3 ,0x209bbd86 ,0x7 )
+ TEST_D_ED(pack, 195, 0x803d04a8, 0x3d04a871 ,0x50637a2d ,0x86ec2f85 )
+ TEST_D_D(parity, 196, 0x101, 0x6033fd4c )
+ TEST_D_D(popcnt.w, 197, 0x15, 0xed7dcbc6 )
+ TEST_D_DI(rsub, 198, 0x4ee91cd3, 0xb116e3bc ,0x8f )
+ TEST_D_DI(rsubs, 199, 0x923eddd7, 0x6dc122fb ,0xd2 )
+ TEST_D_DI(rsubs.u, 200, 0x0, 0xeea32363 ,0xae )
+ TEST_D_D(sat.b, 201, 0xffffff80, 0x9933174e )
+ TEST_D_D(sat.bu, 202, 0xff, 0x917808d7 )
+ TEST_D_D(sat.h, 203, 0xffff8000, 0xa6d33749 )
+ TEST_D_D(sat.hu, 204, 0xffff, 0x534af788 )
+ TEST_D_DDI(sel, 205, 0x620aac73, 0xf617d4dc ,0x620aac73 ,0x53 )
+ TEST_D_DDD(sel, 206, 0x133a028, 0xb8a3faae ,0x133a028 ,0x9042e62e )
+ TEST_D_DDI(seln, 207, 0x8, 0x4a449741 ,0x5354950a ,0x8 )
+ TEST_D_DDD(seln, 208, 0x4f8b1cda, 0x9e3173c3 ,0x4a6f65e9 ,0x4f8b1cda )
+ TEST_D_DI(sh, 209, 0x97000000, 0x56ffbcb8 ,0xd5 )
+ TEST_D_DD(sh, 210, 0x225, 0x112c2fff ,0x5f7f64ad )
+ TEST_D_I(sh, 211, 0x0, 0x6 )
+ TEST_D_DIDI(sh.and.t, 212, 0x1, 0xfba22cf9 ,0x5 ,0xfda859c ,0x6 )
+ TEST_D_DIDI(sh.andn.t, 213, 0x1, 0xf22e1491 ,0x7 ,0x23ac3c36 ,0x3 )
+ TEST_D_DI(sh.eq, 214, 0x0, 0xda3960 ,0x9d )
+ TEST_D_DD(sh.eq, 215, 0x0, 0xf76d811e ,0x6eaa1a5e )
+ TEST_D_DI(sh.ge, 216, 0x0, 0xbb006b34 ,0x4 )
+ TEST_D_DD(sh.ge, 217, 0x0, 0xee02bc23 ,0xdaf2111 )
+ TEST_D_DI(sh.ge.u, 218, 0x1, 0xc8909dce ,0x53 )
+ TEST_D_DD(sh.ge.u, 219, 0x1, 0x5ebe1b63 ,0x2c380da6 )
+ TEST_D_DI(sh.h, 220, 0x32002d00, 0x6032a92d ,0xc8 )
+ TEST_D_DD(sh.h, 221, 0x780878, 0xc00fc10f ,0x670e07a3 )
+ TEST_D_DI(sh.lt, 222, 0x1, 0xd55620a0 ,0x28 )
+ TEST_D_DD(sh.lt, 223, 0x1, 0xbab4c4f8 ,0xd6b23303 )
+ TEST_D_DI(sh.lt.u, 224, 0x0, 0x6d1e8ad ,0xbb )
+ TEST_D_DD(sh.lt.u, 225, 0x1, 0xbdc4998 ,0x660a4b5f )
+ TEST_D_DIDI(sh.nand.t, 226, 0x1, 0xfb3bb8d0 ,0x3 ,0x237800c5 ,0x3 )
+ TEST_D_DI(sh.ne, 227, 0x1, 0x5e6bff56 ,0x83 )
+ TEST_D_DD(sh.ne, 228, 0x1, 0x5f53e44b ,0x4aaa9437 )
+ TEST_D_DIDI(sh.nor.t, 229, 0x0, 0x6ee37832 ,0x6 ,0x6296e652 ,0x5 )
+ TEST_D_DIDI(sh.or.t, 230, 0x1, 0xc6079a4e ,0x6 ,0xa81b155a ,0x1 )
+ TEST_D_DIDI(sh.orn.t, 231, 0x1, 0x188eb9ff ,0x6 ,0x35916e9 ,0x2 )
+ TEST_D_DIDI(sh.xnor.t, 232, 0x1, 0x4babd924 ,0x1 ,0x6f28e657 ,0x6 )
+ TEST_D_DIDI(sh.xor.t, 233, 0x0, 0x759dfc75 ,0x3 ,0xac541f56 ,0x3 )
+ TEST_D_DI(sha, 234, 0xb69145c0, 0x62da4517 ,0x46 )
+ TEST_D_DD(sha, 235, 0xccd8e400, 0x25333639 ,0xb4e65a0a )
+ TEST_D_I(sha, 236, 0x0, 0x5 )
+ TEST_D_DI(sha.h, 237, 0xf8404f80, 0x8fe1d53e ,0x6 )
+ TEST_D_DD(sha.h, 238, 0x10006000, 0x84010b96 ,0xc20875ac )
+ TEST_D_DI(shas, 239, 0x7fffffff, 0x539952ab ,0x1f )
+ TEST_D_DD(shas, 240, 0x20b5a5, 0x416b4be8 ,0x11eb83b7 )
TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 08/10] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (6 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 07/10] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 09/10] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 10/10] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/test_arith.S | 34 ++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index 728509cfa9..02637f89f9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -242,5 +242,39 @@ _start:
TEST_D_DD(sha.h, 238, 0x10006000, 0x84010b96 ,0xc20875ac )
TEST_D_DI(shas, 239, 0x7fffffff, 0x539952ab ,0x1f )
TEST_D_DD(shas, 240, 0x20b5a5, 0x416b4be8 ,0x11eb83b7 )
+ TEST_D_DI(shuffle, 241, 0xed28c9ed, 0x28e9edc9 ,0x71 )
+ TEST_D_DD(sub, 242, 0x3806b676, 0x56f5e4bc ,0x1eef2e46 )
+ TEST_D_D(sub, 243, 0xc98e16b7, 0x3671e949 )
+ TEST_D_D15D(sub, 244, 0xf5bbbabd, 0x6a8db6c ,0x10ed20af )
+ TEST_D15_DD(sub, 245, 0x5618f5a0, 0xa6342636 ,0x501b3096 )
+ TEST_D_DD(sub.b, 246, 0x9ced6d25, 0x28dbb9ee ,0x8cee4cc9 )
+ TEST_D_DD(sub.h, 247, 0xc80b12d0, 0xbe0897d3 ,0xf5fd8503 )
+ TEST_D_DD(subc, 248, 0xbeeccedb, 0x2164d45a ,0x6278057e )
+ TEST_D_DD(subs, 249, 0x90d370bc, 0x95060d13 ,0x4329c57 )
+ TEST_D_D(subs, 250, 0xd89c4149, 0x2763beb7 )
+ TEST_D_DD(subs.h, 251, 0xad93dfea, 0x2c97e0d1 ,0x7f0400e7 )
+ TEST_D_DD(subs.hu, 252, 0x33f6, 0xa768372d ,0xc80b0337 )
+ TEST_D_DD(subs.u, 253, 0x0, 0x7084c694 ,0x90c2f594 )
+ TEST_D_DD(subx, 254, 0xd19a2948, 0x7c40dcf9 ,0xaaa6b3b1 )
+ TEST_E_D(unpack, 255, 0x6405b000 ,0xffffffa5, 0x12480b60 )
+ TEST_D_DI(xnor, 256, 0x83b45e8d, 0x7c4ba167 ,0x15 )
+ TEST_D_DD(xnor, 257, 0x6808b995, 0x2fdb8402 ,0xb82cc268 )
+ TEST_D_DIDI(xnor.t, 258, 0x1, 0x490ac395 ,0x6 ,0x6c41105b ,0x6 )
+ TEST_D_DI(xor, 259, 0x2f27c804, 0x2f27c860 ,0x64 )
+ TEST_D_DD(xor, 260, 0xa020af5b, 0x67f62bea ,0xc7d684b1 )
+ TEST_D_D(xor, 261, 0xbc28874, 0xbc28874 )
+ TEST_D_DI(xor.eq, 262, 0x0, 0xee9e03cc ,0x7b )
+ TEST_D_DD(xor.eq, 263, 0x0, 0x74f79928 ,0x2d3ec476 )
+ TEST_D_DI(xor.ge, 264, 0x0, 0xcf2296f1 ,0xf0 )
+ TEST_D_DD(xor.ge, 265, 0x0, 0xf9915543 ,0x20cb6ab7 )
+ TEST_D_DI(xor.ge.u, 266, 0x1, 0xaa8a78f6 ,0xce )
+ TEST_D_DD(xor.ge.u, 267, 0x0, 0x94e9f87 ,0xab43f3ce )
+ TEST_D_DI(xor.lt, 268, 0x0, 0x3412e315 ,0xcb )
+ TEST_D_DD(xor.lt, 269, 0x1, 0x5571b703 ,0x6a9008a3 )
+ TEST_D_DI(xor.lt.u, 270, 0x0, 0x66a0a3c0 ,0xe1 )
+ TEST_D_DD(xor.lt.u, 271, 0x0, 0xa66deb02 ,0x7dd7b425 )
+ TEST_D_DI(xor.ne, 272, 0x1, 0x147b3e3a ,0xfa )
+ TEST_D_DD(xor.ne, 273, 0x1, 0x92147ec0 ,0xa697f601 )
+ TEST_D_DIDI(xor.t, 274, 0x0, 0xed9ea075 ,0x7 ,0x13f5d03c ,0x7 )
TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 09/10] target/tricore: Remove CSFRs from cpu.h
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (7 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 08/10] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 10/10] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++----------------------------------------
1 file changed, 9 insertions(+), 134 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 3708405be8..1cace96b01 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -30,150 +30,25 @@ typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
uint32_t gpr_d[16];
- /* CSFR Register */
- uint32_t PCXI;
/* Frequently accessed PSW_USB bits are stored separately for efficiency.
This contains all the other bits. Use psw_{read,write} to access
the whole PSW. */
uint32_t PSW;
-
- /* PSW flag cache for faster execution
- */
+ /* PSW flag cache for faster execution */
uint32_t PSW_USB_C;
uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
- uint32_t PC;
- uint32_t SYSCON;
- uint32_t CPU_ID;
- uint32_t CORE_ID;
- uint32_t BIV;
- uint32_t BTV;
- uint32_t ISP;
- uint32_t ICR;
- uint32_t FCX;
- uint32_t LCX;
- uint32_t COMPAT;
-
- /* Mem Protection Register */
- uint32_t DPR0_0L;
- uint32_t DPR0_0U;
- uint32_t DPR0_1L;
- uint32_t DPR0_1U;
- uint32_t DPR0_2L;
- uint32_t DPR0_2U;
- uint32_t DPR0_3L;
- uint32_t DPR0_3U;
-
- uint32_t DPR1_0L;
- uint32_t DPR1_0U;
- uint32_t DPR1_1L;
- uint32_t DPR1_1U;
- uint32_t DPR1_2L;
- uint32_t DPR1_2U;
- uint32_t DPR1_3L;
- uint32_t DPR1_3U;
-
- uint32_t DPR2_0L;
- uint32_t DPR2_0U;
- uint32_t DPR2_1L;
- uint32_t DPR2_1U;
- uint32_t DPR2_2L;
- uint32_t DPR2_2U;
- uint32_t DPR2_3L;
- uint32_t DPR2_3U;
-
- uint32_t DPR3_0L;
- uint32_t DPR3_0U;
- uint32_t DPR3_1L;
- uint32_t DPR3_1U;
- uint32_t DPR3_2L;
- uint32_t DPR3_2U;
- uint32_t DPR3_3L;
- uint32_t DPR3_3U;
-
- uint32_t CPR0_0L;
- uint32_t CPR0_0U;
- uint32_t CPR0_1L;
- uint32_t CPR0_1U;
- uint32_t CPR0_2L;
- uint32_t CPR0_2U;
- uint32_t CPR0_3L;
- uint32_t CPR0_3U;
-
- uint32_t CPR1_0L;
- uint32_t CPR1_0U;
- uint32_t CPR1_1L;
- uint32_t CPR1_1U;
- uint32_t CPR1_2L;
- uint32_t CPR1_2U;
- uint32_t CPR1_3L;
- uint32_t CPR1_3U;
-
- uint32_t CPR2_0L;
- uint32_t CPR2_0U;
- uint32_t CPR2_1L;
- uint32_t CPR2_1U;
- uint32_t CPR2_2L;
- uint32_t CPR2_2U;
- uint32_t CPR2_3L;
- uint32_t CPR2_3U;
-
- uint32_t CPR3_0L;
- uint32_t CPR3_0U;
- uint32_t CPR3_1L;
- uint32_t CPR3_1U;
- uint32_t CPR3_2L;
- uint32_t CPR3_2U;
- uint32_t CPR3_3L;
- uint32_t CPR3_3U;
-
- uint32_t DPM0;
- uint32_t DPM1;
- uint32_t DPM2;
- uint32_t DPM3;
-
- uint32_t CPM0;
- uint32_t CPM1;
- uint32_t CPM2;
- uint32_t CPM3;
-
- /* Memory Management Registers */
- uint32_t MMU_CON;
- uint32_t MMU_ASI;
- uint32_t MMU_TVA;
- uint32_t MMU_TPA;
- uint32_t MMU_TPX;
- uint32_t MMU_TFA;
- /* {1.3.1 only */
- uint32_t BMACON;
- uint32_t SMACON;
- uint32_t DIEAR;
- uint32_t DIETR;
- uint32_t CCDIER;
- uint32_t MIECON;
- uint32_t PIEAR;
- uint32_t PIETR;
- uint32_t CCPIER;
- /*} */
- /* Debug Registers */
- uint32_t DBGSR;
- uint32_t EXEVT;
- uint32_t CREVT;
- uint32_t SWEVT;
- uint32_t TR0EVT;
- uint32_t TR1EVT;
- uint32_t DMS;
- uint32_t DCX;
- uint32_t DBGTCR;
- uint32_t CCTRL;
- uint32_t CCNT;
- uint32_t ICNT;
- uint32_t M1CNT;
- uint32_t M2CNT;
- uint32_t M3CNT;
+#define R(ADDR, NAME, FEATURE) uint32_t NAME;
+#define A(ADDR, NAME, FEATURE) uint32_t NAME;
+#define E(ADDR, NAME, FEATURE) uint32_t NAME;
+#include "csfr.h.inc"
+#undef R
+#undef A
+#undef E
+
/* Floating Point Registers */
float_status fp_status;
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 10/10] target/tricore: Change effective address (ea) to target_ulong
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
` (8 preceding siblings ...)
2023-09-13 10:53 ` [PATCH 09/10] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
@ 2023-09-13 10:53 ` Bastian Koppelmann
9 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-09-13 10:53 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
as this is an effective address and those cannot be signed,
it should not be a signed integed.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 0cf8eb50bd..ba9c4444b3 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2458,7 +2458,7 @@ static bool cdc_zero(target_ulong *psw)
return count == 0;
}
-static void save_context_upper(CPUTriCoreState *env, int ea)
+static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, psw_read(env));
@@ -2478,7 +2478,7 @@ static void save_context_upper(CPUTriCoreState *env, int ea)
cpu_stl_data(env, ea+60, env->gpr_d[15]);
}
-static void save_context_lower(CPUTriCoreState *env, int ea)
+static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, env->gpr_a[11]);
@@ -2498,7 +2498,7 @@ static void save_context_lower(CPUTriCoreState *env, int ea)
cpu_stl_data(env, ea+60, env->gpr_d[7]);
}
-static void restore_context_upper(CPUTriCoreState *env, int ea,
+static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
target_ulong *new_PCXI, target_ulong *new_PSW)
{
*new_PCXI = cpu_ldl_data(env, ea);
@@ -2519,7 +2519,7 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
}
-static void restore_context_lower(CPUTriCoreState *env, int ea,
+static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
target_ulong *ra, target_ulong *pcxi)
{
*pcxi = cpu_ldl_data(env, ea);
@@ -2763,26 +2763,26 @@ void helper_rfm(CPUTriCoreState *env)
}
}
-void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
+void helper_ldlcx(CPUTriCoreState *env, target_ulong ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and RA */
restore_context_lower(env, ea, &dummy, &dummy);
}
-void helper_lducx(CPUTriCoreState *env, uint32_t ea)
+void helper_lducx(CPUTriCoreState *env, target_ulong ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and PSW */
restore_context_upper(env, ea, &dummy, &dummy);
}
-void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
+void helper_stlcx(CPUTriCoreState *env, target_ulong ea)
{
save_context_lower(env, ea);
}
-void helper_stucx(CPUTriCoreState *env, uint32_t ea)
+void helper_stucx(CPUTriCoreState *env, target_ulong ea)
{
save_context_upper(env, ea);
}
--
2.42.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-09-13 10:55 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-13 10:53 [PATCH 00/10] TriCore tests and cleanups Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 01/10] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 02/10] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 03/10] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 04/10] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 05/10] tests/tcg/tricore: Add test for and to csub Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 06/10] tests/tcg/tricore: Add from dextr to lt Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 07/10] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 08/10] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 09/10] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-13 10:53 ` [PATCH 10/10] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
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