[PATCH 0/1] sbsa-ref: add non-secure EL2 virtual timer

[PATCH 0/1] sbsa-ref: add non-secure EL2 virtual timer

[Marcin Juszkiewicz]

Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure
EL2 virtual timer.

This change adds it to fullfil Arm BSA (Base System Architecture)
requirements.

From firmware side information about timer needs to be present in GTDT
acpi table. If it is there with suggested interrupt 28 then BSA ACS test
266 passes:

--------------------------------------------------------------
 226 : Check NS EL2-Virt timer PPI Assignment         START

       Received vir el2 interrupt
       B_PPI_02
                                       : Result:  PASS
         END
--------------------------------------------------------------

On Armv8.0 cpus this timer should not exist as there is no VHE.

I hope this code is correct. Tried to compare with other emulation
targets but only "virt" and "sbsa-ref" use cpu cores newer than v8.0
ones.

Marcin Juszkiewicz (1):
  sbsa-ref: add non-secure EL2 virtual timer

 hw/arm/sbsa-ref.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.41.0

[PATCH 1/1] sbsa-ref: add non-secure EL2 virtual timer

[Marcin Juszkiewicz]

Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure
EL2 virtual timer.

This change adds it to fullfil Arm BSA (Base System Architecture)
requirements.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

---
 hw/arm/sbsa-ref.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index bc89eb4806..3c7dfcd6dc 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -61,6 +61,7 @@
 #define ARCH_TIMER_S_EL1_IRQ   13
 #define ARCH_TIMER_NS_EL1_IRQ  14
 #define ARCH_TIMER_NS_EL2_IRQ  10
+#define ARCH_TIMER_NS_EL2_VIRT_IRQ  12
 
 enum {
     SBSA_FLASH,
@@ -489,6 +490,7 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
+            [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
         };
 
         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
-- 
2.41.0

Re: [PATCH 1/1] sbsa-ref: add non-secure EL2 virtual timer

[Peter Maydell]

On Wed, 13 Sept 2023 at 15:06, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure
> EL2 virtual timer.
>
> This change adds it to fullfil Arm BSA (Base System Architecture)
> requirements.
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>
> ---
>  hw/arm/sbsa-ref.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index bc89eb4806..3c7dfcd6dc 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -61,6 +61,7 @@
>  #define ARCH_TIMER_S_EL1_IRQ   13
>  #define ARCH_TIMER_NS_EL1_IRQ  14
>  #define ARCH_TIMER_NS_EL2_IRQ  10
> +#define ARCH_TIMER_NS_EL2_VIRT_IRQ  12
>
>  enum {
>      SBSA_FLASH,
> @@ -489,6 +490,7 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
>              [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
>              [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
>              [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
> +            [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
>          };
>
>          for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
> --

This is correct, so I've applied it to target-arm.next. We also
need something similar for the virt board (where there is an
additional complication that we need to also report it in the dtb
and the ACPI tables, ideally only if the CPU has the feature).

thanks
-- PMM