From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org, "Michael Tsirkin" <mst@redhat.com>,
"Fan Ni" <fan.ni@samsung.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: <linuxarm@huawei.com>
Subject: [PATCH 2/4] hw/cxl: Use available size parameter to index into register arrays.
Date: Wed, 13 Sep 2023 16:05:19 +0100 [thread overview]
Message-ID: <20230913150521.30035-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230913150521.30035-1-Jonathan.Cameron@huawei.com>
Indexing has to be done into an array with the right size elements.
As such, the size parameter always matches the array element size
and can be used in place of the longer sizeof(*array)
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-component-utils.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index f3bbf0fd13..089e10b232 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -76,7 +76,7 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
if (cregs->special_ops && cregs->special_ops->read) {
return cregs->special_ops->read(cxl_cstate, offset, size);
} else {
- return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
+ return cregs->cache_mem_registers[offset / size];
}
}
@@ -122,10 +122,10 @@ static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
"CXL 8 byte cache mem registers not implemented\n");
return;
}
- mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)];
+ mask = cregs->cache_mem_regs_write_mask[offset / size];
value &= mask;
/* RO bits should remain constant. Done by reading existing value */
- value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
+ value |= ~mask & cregs->cache_mem_registers[offset / size];
if (cregs->special_ops && cregs->special_ops->write) {
cregs->special_ops->write(cxl_cstate, offset, value, size);
return;
@@ -135,7 +135,7 @@ static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
offset <= A_CXL_HDM_DECODER3_TARGET_LIST_HI) {
dumb_hdm_handler(cxl_cstate, offset, value);
} else {
- cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
+ cregs->cache_mem_registers[offset / size] = value;
}
}
--
2.39.2
next prev parent reply other threads:[~2023-09-13 15:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-13 15:05 [PATCH 0/4] hw/cxl: Line length reduction and related Jonathan Cameron via
2023-09-13 15:05 ` [PATCH 1/4] hw/cxl: Use a switch to explicitly check size in caps_reg_read() Jonathan Cameron via
2023-09-13 15:13 ` Philippe Mathieu-Daudé
2023-09-13 15:05 ` Jonathan Cameron via [this message]
2023-09-14 12:54 ` [PATCH 2/4] hw/cxl: Use available size parameter to index into register arrays Michael Tokarev
2023-09-18 12:29 ` Jonathan Cameron via
2023-09-13 15:05 ` [PATCH 3/4] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Jonathan Cameron via
2023-09-14 5:44 ` Philippe Mathieu-Daudé
2023-09-13 15:05 ` [PATCH 4/4] hw/cxl: Line length reductions Jonathan Cameron via
2023-09-14 12:57 ` Michael Tokarev
2023-09-15 17:01 ` Jonathan Cameron via
2023-09-15 17:07 ` Jonathan Cameron via
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