From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Babu Moger <babu.moger@amd.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v4 17/21] i386: Add cache topology info in CPUCacheInfo
Date: Thu, 14 Sep 2023 15:21:55 +0800 [thread overview]
Message-ID: <20230914072159.1177582-18-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20230914072159.1177582-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a specific cpu topology, such
as the connection between L2 cache and core level, and the connection
between L3 cache and die level.
In fact, the settings of these topologies depend on the specific
platform and are not static. For example, on Alder Lake-P, every
four Atom cores share the same L2 cache.
Thus, we should explicitly define the corresponding cache topology for
different cache models to increase scalability.
Except legacy_l2_cache_cpuid2 (its default topo level is
CPU_TOPO_LEVEL_UNKNOW), explicitly set the corresponding topology level
for all other cache models. In order to be compatible with the existing
cache topology, set the CPU_TOPO_LEVEL_CORE level for the i/d cache, set
the CPU_TOPO_LEVEL_CORE level for L2 cache, and set the
CPU_TOPO_LEVEL_DIE level for L3 cache.
The field for CPUID[4].EAX[bits 25:14] or CPUID[0x8000001D].EAX[bits
25:14] will be set based on CPUCacheInfo.share_level.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since v3:
* Fix cache topology uninitialization bugs for some AMD CPUs. (Babu)
* Move the CPUTopoLevel enumeration definition to the previous 0x1f
rework patch.
Changes since v1:
* Add the prefix "CPU_TOPO_LEVEL_*" for CPU topology level names.
(Yanan)
* (Revert, pls refer "i386: Decouple CPUID[0x1F] subleaf with specific
topology level") Rename the "INVALID" level to CPU_TOPO_LEVEL_UNKNOW.
(Yanan)
---
target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 7 +++++++
2 files changed, 43 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d8c5e774cf95..fcb4f4da3431 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -557,6 +557,7 @@ static CPUCacheInfo legacy_l1d_cache = {
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@@ -571,6 +572,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = {
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
};
/* L1 instruction cache: */
@@ -584,6 +586,7 @@ static CPUCacheInfo legacy_l1i_cache = {
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@@ -598,6 +601,7 @@ static CPUCacheInfo legacy_l1i_cache_amd = {
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
};
/* Level 2 unified cache: */
@@ -611,6 +615,7 @@ static CPUCacheInfo legacy_l2_cache = {
.sets = 4096,
.partitions = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
};
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
@@ -620,6 +625,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 = {
.size = 2 * MiB,
.line_size = 64,
.associativity = 8,
+ .share_level = CPU_TOPO_LEVEL_INVALID,
};
@@ -633,6 +639,7 @@ static CPUCacheInfo legacy_l2_cache_amd = {
.associativity = 16,
.sets = 512,
.partitions = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
};
/* Level 3 unified cache: */
@@ -648,6 +655,7 @@ static CPUCacheInfo legacy_l3_cache = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
+ .share_level = CPU_TOPO_LEVEL_DIE,
};
/* TLB definitions: */
@@ -1944,6 +1952,7 @@ static const CPUCaches epyc_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -1956,6 +1965,7 @@ static const CPUCaches epyc_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -1966,6 +1976,7 @@ static const CPUCaches epyc_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -1979,6 +1990,7 @@ static const CPUCaches epyc_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
@@ -1994,6 +2006,7 @@ static CPUCaches epyc_v4_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2006,6 +2019,7 @@ static CPUCaches epyc_v4_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2016,6 +2030,7 @@ static CPUCaches epyc_v4_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2029,6 +2044,7 @@ static CPUCaches epyc_v4_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
@@ -2044,6 +2060,7 @@ static const CPUCaches epyc_rome_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2056,6 +2073,7 @@ static const CPUCaches epyc_rome_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2066,6 +2084,7 @@ static const CPUCaches epyc_rome_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2079,6 +2098,7 @@ static const CPUCaches epyc_rome_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
@@ -2094,6 +2114,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2106,6 +2127,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2116,6 +2138,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2129,6 +2152,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
@@ -2144,6 +2168,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2156,6 +2181,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2166,6 +2192,7 @@ static const CPUCaches epyc_milan_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2179,6 +2206,7 @@ static const CPUCaches epyc_milan_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
@@ -2194,6 +2222,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2206,6 +2235,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2216,6 +2246,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2229,6 +2260,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
@@ -2244,6 +2276,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2256,6 +2289,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2266,6 +2300,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.partitions = 1,
.sets = 2048,
.lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2279,6 +2314,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
+ .share_level = CPU_TOPO_LEVEL_DIE,
},
};
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index fa1452380882..a13132007415 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1596,6 +1596,13 @@ typedef struct CPUCacheInfo {
* address bits. CPUID[4].EDX[bit 2].
*/
bool complex_indexing;
+
+ /*
+ * Cache Topology. The level that cache is shared in.
+ * Used to encode CPUID[4].EAX[bits 25:14] or
+ * CPUID[0x8000001D].EAX[bits 25:14].
+ */
+ enum CPUTopoLevel share_level;
} CPUCacheInfo;
--
2.34.1
next prev parent reply other threads:[~2023-09-14 7:17 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 7:21 [PATCH v4 00/21] Support smp.clusters for x86 in QEMU Zhao Liu
2023-09-14 7:21 ` [PATCH v4 01/21] i386: Fix comment style in topology.h Zhao Liu
2023-09-22 16:05 ` Moger, Babu
2023-09-26 3:11 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 02/21] tests: Rename test-x86-cpuid.c to test-x86-topo.c Zhao Liu
2023-09-14 7:21 ` [PATCH v4 03/21] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-09-14 7:31 ` Philippe Mathieu-Daudé
2023-09-15 7:39 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 04/21] hw/cpu: Update the comments of nr_cores and nr_dies Zhao Liu
2023-09-14 7:32 ` Philippe Mathieu-Daudé
2023-09-15 7:40 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-09-14 7:21 ` [PATCH v4 06/21] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 07/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-09-14 7:21 ` [PATCH v4 08/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 09/21] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2023-09-14 7:21 ` [PATCH v4 10/21] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-09-14 7:38 ` Philippe Mathieu-Daudé
2023-09-15 7:50 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 11/21] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-09-14 7:21 ` [PATCH v4 12/21] i386: Expose module level in CPUID[0x1F] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 13/21] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-09-14 7:21 ` [PATCH v4 14/21] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-09-14 7:21 ` [PATCH v4 15/21] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-09-14 7:21 ` [PATCH v4 16/21] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-09-14 7:21 ` Zhao Liu [this message]
2023-09-14 7:21 ` [PATCH v4 18/21] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 19/21] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-09-22 19:27 ` Moger, Babu
2023-09-26 3:10 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 20/21] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-09-22 19:27 ` Moger, Babu
2023-09-26 3:08 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H Zhao Liu
2023-09-14 7:41 ` Philippe Mathieu-Daudé
2023-09-15 7:53 ` Zhao Liu
2023-10-03 12:57 ` Michael S. Tsirkin
2023-10-06 16:36 ` Zhao Liu
2023-10-18 14:12 ` Zhao Liu
2023-09-22 16:03 ` [PATCH v4 00/21] Support smp.clusters for x86 in QEMU Moger, Babu
2023-09-26 3:11 ` Zhao Liu
2023-10-18 12:06 ` Michael S. Tsirkin
2023-10-18 14:08 ` Zhao Liu
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