From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Babu Moger <babu.moger@amd.com>, Zhao Liu <zhao1.liu@intel.com>,
Robert Hoo <robert.hu@linux.intel.com>
Subject: [PATCH v4 07/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()
Date: Thu, 14 Sep 2023 15:21:45 +0800 [thread overview]
Message-ID: <20230914072159.1177582-8-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20230914072159.1177582-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone
to confusion and mistakes.
And the structure X86CPUTopoInfo names its members clearly, thus the
variable "topo_info" should be preferred.
In addition, in cpu_x86_cpuid(), to uniformly use the topology variable,
replace env->dies with topo_info.dies_per_pkg as well.
Suggested-by: Robert Hoo <robert.hu@linux.intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since v3:
* Fix typo. (Babu)
Changes since v1:
* Extract cores_per_socket from the code block and use it as a local
variable for cpu_x86_cpuid(). (Yanan)
* Remove vcpus_per_socket variable and use cpus_per_pkg directly.
(Yanan)
* Replace env->dies with topo_info.dies_per_pkg in cpu_x86_cpuid().
---
target/i386/cpu.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a3d67c1762c0..0e9a33034026 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6012,11 +6012,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t limit;
uint32_t signature[3];
X86CPUTopoInfo topo_info;
+ uint32_t cores_per_pkg;
+ uint32_t cpus_per_pkg;
topo_info.dies_per_pkg = env->nr_dies;
topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
topo_info.threads_per_core = cs->nr_threads;
+ cores_per_pkg = topo_info.cores_per_die * topo_info.dies_per_pkg;
+ cpus_per_pkg = cores_per_pkg * topo_info.threads_per_core;
+
/* Calculate & apply limits for different index ranges */
if (index >= 0xC0000000) {
limit = env->cpuid_xlevel2;
@@ -6052,8 +6057,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx |= CPUID_EXT_OSXSAVE;
}
*edx = env->features[FEAT_1_EDX];
- if (cs->nr_cores * cs->nr_threads > 1) {
- *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
+ if (cpus_per_pkg > 1) {
+ *ebx |= cpus_per_pkg << 16;
*edx |= CPUID_HT;
}
if (!cpu->enable_pmu) {
@@ -6090,8 +6095,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*/
if (*eax & 31) {
int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
- int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
- if (cs->nr_cores > 1) {
+
+ if (cores_per_pkg > 1) {
int addressable_cores_offset =
apicid_pkg_offset(&topo_info) -
apicid_core_offset(&topo_info);
@@ -6099,7 +6104,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*eax &= ~0xFC000000;
*eax |= (1 << (addressable_cores_offset - 1)) << 26;
}
- if (host_vcpus_per_cache > vcpus_per_socket) {
+ if (host_vcpus_per_cache > cpus_per_pkg) {
int pkg_offset = apicid_pkg_offset(&topo_info);
*eax &= ~0x3FFC000;
@@ -6244,12 +6249,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
switch (count) {
case 0:
*eax = apicid_core_offset(&topo_info);
- *ebx = cs->nr_threads;
+ *ebx = topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
*eax = apicid_pkg_offset(&topo_info);
- *ebx = cs->nr_cores * cs->nr_threads;
+ *ebx = cpus_per_pkg;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
default:
@@ -6270,7 +6275,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 0x1F:
/* V2 Extended Topology Enumeration Leaf */
- if (env->nr_dies < 2) {
+ if (topo_info.dies_per_pkg < 2) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
@@ -6280,7 +6285,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
switch (count) {
case 0:
*eax = apicid_core_offset(&topo_info);
- *ebx = cs->nr_threads;
+ *ebx = topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
@@ -6290,7 +6295,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
- *ebx = cs->nr_cores * cs->nr_threads;
+ *ebx = cpus_per_pkg;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
default:
@@ -6515,7 +6520,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
* discards multiple thread information if it is set.
* So don't set it here for Intel to make Linux guests happy.
*/
- if (cs->nr_cores * cs->nr_threads > 1) {
+ if (cpus_per_pkg > 1) {
if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
@@ -6581,7 +6586,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*eax |= (cpu_x86_virtual_addr_width(env) << 8);
}
*ebx = env->features[FEAT_8000_0008_EBX];
- if (cs->nr_cores * cs->nr_threads > 1) {
+ if (cpus_per_pkg > 1) {
/*
* Bits 15:12 is "The number of bits in the initial
* Core::X86::Apic::ApicId[ApicId] value that indicate
@@ -6589,7 +6594,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
* Bits 7:0 is "The number of threads in the package is NC+1"
*/
*ecx = (apicid_pkg_offset(&topo_info) << 12) |
- ((cs->nr_cores * cs->nr_threads) - 1);
+ (cpus_per_pkg - 1);
} else {
*ecx = 0;
}
--
2.34.1
next prev parent reply other threads:[~2023-09-14 7:14 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 7:21 [PATCH v4 00/21] Support smp.clusters for x86 in QEMU Zhao Liu
2023-09-14 7:21 ` [PATCH v4 01/21] i386: Fix comment style in topology.h Zhao Liu
2023-09-22 16:05 ` Moger, Babu
2023-09-26 3:11 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 02/21] tests: Rename test-x86-cpuid.c to test-x86-topo.c Zhao Liu
2023-09-14 7:21 ` [PATCH v4 03/21] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-09-14 7:31 ` Philippe Mathieu-Daudé
2023-09-15 7:39 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 04/21] hw/cpu: Update the comments of nr_cores and nr_dies Zhao Liu
2023-09-14 7:32 ` Philippe Mathieu-Daudé
2023-09-15 7:40 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-09-14 7:21 ` [PATCH v4 06/21] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-09-14 7:21 ` Zhao Liu [this message]
2023-09-14 7:21 ` [PATCH v4 08/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 09/21] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2023-09-14 7:21 ` [PATCH v4 10/21] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-09-14 7:38 ` Philippe Mathieu-Daudé
2023-09-15 7:50 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 11/21] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-09-14 7:21 ` [PATCH v4 12/21] i386: Expose module level in CPUID[0x1F] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 13/21] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-09-14 7:21 ` [PATCH v4 14/21] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-09-14 7:21 ` [PATCH v4 15/21] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-09-14 7:21 ` [PATCH v4 16/21] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-09-14 7:21 ` [PATCH v4 17/21] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-09-14 7:21 ` [PATCH v4 18/21] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-09-14 7:21 ` [PATCH v4 19/21] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-09-22 19:27 ` Moger, Babu
2023-09-26 3:10 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 20/21] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-09-22 19:27 ` Moger, Babu
2023-09-26 3:08 ` Zhao Liu
2023-09-14 7:21 ` [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H Zhao Liu
2023-09-14 7:41 ` Philippe Mathieu-Daudé
2023-09-15 7:53 ` Zhao Liu
2023-10-03 12:57 ` Michael S. Tsirkin
2023-10-06 16:36 ` Zhao Liu
2023-10-18 14:12 ` Zhao Liu
2023-09-22 16:03 ` [PATCH v4 00/21] Support smp.clusters for x86 in QEMU Moger, Babu
2023-09-26 3:11 ` Zhao Liu
2023-10-18 12:06 ` Michael S. Tsirkin
2023-10-18 14:08 ` Zhao Liu
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