From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
qemu-stable@nongnu.org
Subject: [PATCH] target/mips: Fix TX79 LQ/SQ opcodes
Date: Thu, 14 Sep 2023 11:04:47 +0200 [thread overview]
Message-ID: <20230914090447.12557-1-philmd@linaro.org> (raw)
The base register address offset is *signed*.
Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/tx79.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index 57d87a2076..578b8c54c0 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -24,7 +24,7 @@
@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
-@ldst ...... base:5 rt:5 offset:16 &i
+@ldst ...... base:5 rt:5 offset:s16 &i
###########################################################################
--
2.41.0
next reply other threads:[~2023-09-14 9:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 9:04 Philippe Mathieu-Daudé [this message]
2023-09-14 13:21 ` [PATCH] target/mips: Fix TX79 LQ/SQ opcodes Richard Henderson
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