* [PATCH 00/16] tests: Add CPU topology related smbios test cases
@ 2023-08-25 3:36 Zhao Liu
2023-08-25 3:36 ` [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers Zhao Liu
` (16 more replies)
0 siblings, 17 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Hi all,
This patchset is the follow up tests of previous topology fixes in
smbios [1].
In this patchset, add these test cases:
1. Add the case to test 2 newly added topology helpers (patch 1):
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
2. Add the cases in bios-tables-test.c to:
* test smbios type4 table count (patch 2-4).
* test smbios type4 core count field (patch 5-7).
* update the test of smbios type4 core count2 field (patch 8-10).
* test smbios type4 thread count (patch 11-13).
* test smbios type4 thread count2 (patch 14-16).
With the above new cases, cover all commits of [1] in test.
[1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
Regards,
Zhao
---
Zhao Liu (16):
tests: test-smp-parse: Add the test for cores/threads per socket
helpers
tests: bios-tables-test: Prepare the ACPI table change for type4 count
test
tests: bios-tables-test: Add test for smbios type4 count
tests: bios-tables-test: Add ACPI table binaries for type4 count test
tests: bios-tables-test: Prepare the ACPI table change for type4 core
count test
tests: bios-tables-test: Add test for smbios type4 core count
tests: bios-tables-test: Add ACPI table binaries for type4 core count
test
tests: bios-tables-test: Prepare the ACPI table change for type4 core
count2 test
tests: bios-tables-test: Extend core count2 test to cover general
topology
tests: bios-tables-test: Update ACPI table binaries for core count2
test
tests: bios-tables-test: Prepare the ACPI table change for type4
thread count test
tests: bios-tables-test: Add test for smbios type4 thread count
tests: bios-tables-test: Add ACPI table binaries for type4 thread
count test
tests: bios-tables-test: Prepare the ACPI table change for type4
thread count2 test
tests: bios-tables-test: Add test for smbios type4 thread count2
tests: bios-tables-test: Add ACPI table binaries for type4 thread
count2 test
tests/data/acpi/q35/APIC.core-count | Bin 0 -> 544 bytes
tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 3238 bytes
tests/data/acpi/q35/APIC.thread-count | Bin 0 -> 544 bytes
tests/data/acpi/q35/APIC.thread-count2 | Bin 0 -> 7398 bytes
tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
tests/data/acpi/q35/DSDT.core-count | Bin 0 -> 12913 bytes
tests/data/acpi/q35/DSDT.core-count2 | Bin 32495 -> 33770 bytes
tests/data/acpi/q35/DSDT.thread-count | Bin 0 -> 12913 bytes
tests/data/acpi/q35/DSDT.thread-count2 | Bin 0 -> 63671 bytes
tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
tests/data/acpi/q35/FACP.core-count | Bin 0 -> 244 bytes
tests/data/acpi/q35/FACP.thread-count | Bin 0 -> 244 bytes
tests/data/acpi/q35/FACP.thread-count2 | Bin 0 -> 244 bytes
tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
tests/qtest/bios-tables-test.c | 118 ++++++++++++++++++++++++-
tests/unit/test-smp-parse.c | 67 +++++++++++---
16 files changed, 169 insertions(+), 16 deletions(-)
create mode 100644 tests/data/acpi/q35/APIC.core-count
create mode 100644 tests/data/acpi/q35/APIC.thread-count
create mode 100644 tests/data/acpi/q35/APIC.thread-count2
create mode 100644 tests/data/acpi/q35/APIC.type4-count
create mode 100644 tests/data/acpi/q35/DSDT.core-count
create mode 100644 tests/data/acpi/q35/DSDT.thread-count
create mode 100644 tests/data/acpi/q35/DSDT.thread-count2
create mode 100644 tests/data/acpi/q35/DSDT.type4-count
create mode 100644 tests/data/acpi/q35/FACP.core-count
create mode 100644 tests/data/acpi/q35/FACP.thread-count
create mode 100644 tests/data/acpi/q35/FACP.thread-count2
create mode 100644 tests/data/acpi/q35/FACP.type4-count
--
2.34.1
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 12:31 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 02/16] tests: bios-tables-test: Prepare the ACPI table change for type4 count test Zhao Liu
` (15 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Use the different ways to calculate cores/threads per socket, so that
the new CPU topology levels won't be missed in these 2 helpes:
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
threads per socket").
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/unit/test-smp-parse.c | 67 ++++++++++++++++++++++++++++++-------
1 file changed, 54 insertions(+), 13 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index fdc39a846ca6..24972666a74d 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -394,20 +394,47 @@ static char *smp_config_to_string(const SMPConfiguration *config)
config->has_maxcpus ? "true" : "false", config->maxcpus);
}
-static char *cpu_topology_to_string(const CpuTopology *topo)
+/* Use the different calculation than machine_topo_get_threads_per_socket(). */
+static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo)
+{
+ /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
+ if (!topo->sockets) {
+ return 0;
+ } else {
+ return topo->max_cpus / topo->sockets;
+ }
+}
+
+/* Use the different calculation than machine_topo_get_cores_per_socket(). */
+static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo)
+{
+ /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
+ if (!topo->threads) {
+ return 0;
+ } else {
+ return cpu_topology_get_threads_per_socket(topo) / topo->threads;
+ }
+}
+
+static char *cpu_topology_to_string(const CpuTopology *topo,
+ unsigned int threads_per_socket,
+ unsigned int cores_per_socket)
{
return g_strdup_printf(
"(CpuTopology) {\n"
- " .cpus = %u,\n"
- " .sockets = %u,\n"
- " .dies = %u,\n"
- " .clusters = %u,\n"
- " .cores = %u,\n"
- " .threads = %u,\n"
- " .max_cpus = %u,\n"
+ " .cpus = %u,\n"
+ " .sockets = %u,\n"
+ " .dies = %u,\n"
+ " .clusters = %u,\n"
+ " .cores = %u,\n"
+ " .threads = %u,\n"
+ " .max_cpus = %u,\n"
+ " .threads_per_socket = %u,\n"
+ " .cores_per_socket = %u,\n"
"}",
topo->cpus, topo->sockets, topo->dies, topo->clusters,
- topo->cores, topo->threads, topo->max_cpus);
+ topo->cores, topo->threads, topo->max_cpus,
+ threads_per_socket, cores_per_socket);
}
static void check_parse(MachineState *ms, const SMPConfiguration *config,
@@ -415,14 +442,26 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
bool is_valid)
{
g_autofree char *config_str = smp_config_to_string(config);
- g_autofree char *expect_topo_str = cpu_topology_to_string(expect_topo);
- g_autofree char *output_topo_str = NULL;
+ g_autofree char *expect_topo_str = NULL, *output_topo_str = NULL;
+ unsigned int expect_threads_per_socket, expect_cores_per_socket;
+ unsigned int ms_threads_per_socket, ms_cores_per_socket;
Error *err = NULL;
+ expect_threads_per_socket =
+ cpu_topology_get_threads_per_socket(expect_topo);
+ expect_cores_per_socket =
+ cpu_topology_get_cores_per_socket(expect_topo);
+ expect_topo_str = cpu_topology_to_string(expect_topo,
+ expect_threads_per_socket,
+ expect_cores_per_socket);
+
/* call the generic parser */
machine_parse_smp_config(ms, config, &err);
- output_topo_str = cpu_topology_to_string(&ms->smp);
+ ms_threads_per_socket = machine_topo_get_threads_per_socket(ms);
+ ms_cores_per_socket = machine_topo_get_cores_per_socket(ms);
+ output_topo_str = cpu_topology_to_string(&ms->smp, ms_threads_per_socket,
+ ms_cores_per_socket);
/* when the configuration is supposed to be valid */
if (is_valid) {
@@ -433,7 +472,9 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
(ms->smp.clusters == expect_topo->clusters) &&
(ms->smp.cores == expect_topo->cores) &&
(ms->smp.threads == expect_topo->threads) &&
- (ms->smp.max_cpus == expect_topo->max_cpus)) {
+ (ms->smp.max_cpus == expect_topo->max_cpus) &&
+ (ms_threads_per_socket == expect_threads_per_socket) &&
+ (ms_cores_per_socket == expect_cores_per_socket)) {
return;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 02/16] tests: bios-tables-test: Prepare the ACPI table change for type4 count test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
2023-08-25 3:36 ` [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count Zhao Liu
` (14 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 count.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.type4-count | 0
tests/data/acpi/q35/DSDT.type4-count | 0
tests/data/acpi/q35/FACP.type4-count | 0
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.type4-count
create mode 100644 tests/data/acpi/q35/DSDT.type4-count
create mode 100644 tests/data/acpi/q35/FACP.type4-count
diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..0ce6f8fc72ee 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.type4-count",
+"tests/data/acpi/q35/DSDT.type4-count",
+"tests/data/acpi/q35/FACP.type4-count",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
2023-08-25 3:36 ` [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers Zhao Liu
2023-08-25 3:36 ` [PATCH 02/16] tests: bios-tables-test: Prepare the ACPI table change for type4 count test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 12:54 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test Zhao Liu
` (13 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
calculation").
Test the count of type4 tables for multiple sockets case.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/qtest/bios-tables-test.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 47ba20b9579b..8679255449cf 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -97,6 +97,7 @@ typedef struct {
uint16_t smbios_core_count2;
uint8_t *required_struct_types;
int required_struct_types_len;
+ int type4_count;
QTestState *qts;
} test_data;
@@ -673,12 +674,21 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
}
}
+static void smbios_type4_count_test(test_data *data, int type4_count)
+{
+ int expected_type4_count = data->type4_count;
+
+ if (expected_type4_count) {
+ g_assert_cmpuint(type4_count, ==, expected_type4_count);
+ }
+}
+
static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
{
DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
SmbiosEntryPoint *ep_table = &data->smbios_ep_table;
- int i = 0, len, max_len = 0;
+ int i = 0, len, max_len = 0, type4_count = 0;
uint8_t type, prv, crt;
uint64_t addr;
@@ -704,6 +714,7 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
if (type == 4) {
smbios_cpu_test(data, addr, ep_type);
+ type4_count++;
}
/* seek to end of unformatted string area of this struct ("\0\0") */
@@ -747,6 +758,8 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
for (i = 0; i < data->required_struct_types_len; i++) {
g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
}
+
+ smbios_type4_count_test(data, type4_count);
}
static void test_acpi_load_tables(test_data *data)
@@ -970,6 +983,22 @@ static void test_acpi_q35_tcg(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_type4_count(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".type4-count",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .type4_count = 5,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp cpus=100,maxcpus=120,sockets=5,"
+ "dies=2,cores=4,threads=3", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_core_count2(void)
{
test_data data = {
@@ -2135,6 +2164,8 @@ int main(int argc, char *argv[])
if (has_kvm) {
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
+ qtest_add_func("acpi/q35/type4-count",
+ test_acpi_q35_tcg_type4_count);
qtest_add_func("acpi/q35/core-count2",
test_acpi_q35_tcg_core_count2);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (2 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 13:05 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 05/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core " Zhao Liu
` (12 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
4 files changed, 3 deletions(-)
diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ab60a6ef065d8ce53ae93d311d3777d2d4afb9f6 100644
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literal 0
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diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..edc23198cdb47a981bcbc82bc8e392b815abb554 100644
GIT binary patch
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zN{UiaRFVd8p+X_S@`g*=(yfxVP|_Aj8pJgUg#;@bE@|s7m9&+Two1|vE>9>VSk!Py
z+jgs@ZIrZ4l7``ei%Qx~NZZ*~O8Ty{oszao(g<9DQAs-pX~$l*rX7^DLz0rPqd_Hg
z5mHyLO6sDdE=fwk1savKlaO}qS4lf5X{RLFaKT0;brVwe0hQEEN!^l^h6^|<X%`{w
zI;fI%QPM6+%D@F3m9(3Xb{|$ryD4e6BxT_Ok4oA@NPCW`q&<|h$0a3VJvym}ka~`)
zq#jD@k)-%uowS#b_8wPBdnswJBqe%vQZFI(o={1>l+-IpefxCMK0?}eQYG!9q<xaq
zzh5WqC#3x`m9(Fd_Dj;h0iAS!kPfg<q4X7efRYYK(%?azbdZn^Ce)e^Qqn<58akwt
z4iVC!ewB2Hk`77I@L`>Fn2-(+sHDS`bXbx`j_9N#gmh$3B^{xpBa)Ons*{cq($Qg+
zbd-{gN>b{WPC7<N$3|4rF-kfnN%nD_bexcmpH@l7De1T*rBCRj6NGf)tV%jTNhc&J
zb5bXrB&3t)RMJUGIw?unQ#$DsA)Pv}l1@?5DVNkIzRr2ROTk8dcXGxqs-zet#Uv>n
z*K3LsQaq`W;*=DZq(nj|B?u{zQb`F)N=Q;)pHAu{q`tID>Z7DSN$T&{N&SS>pHWHu
zl+-Ut0|Po~fRF~@S^<2NA>XA2C}}{F1_yQ0AR!IrRMH?N4NB6`kWLyRq@lb@8lt2j
zNg5v3NyCIRJf@O{DQQ@eMn-hf2qBG3sH71}8j+;rX`OVMkWLp=(rHRMElH^}I_V4{
zotacgXDI26B-v+m(pf?}TU1GBDe0^vrO)Z4bA)tmN+q46q;ry#Ij@t>6VmyTN;*$T
z=Orn7K_^`xqzlt3=>jEPa7q2Ki#q8dAzhqNNf#;Uq9nzWItebByYF<#%PJ{JNl8gc
zq;wKoEq6(&t11aMvAF9`DM{+HbrM`CcS-g&m4y3IT#_wG{b`*9*T`K``npQOttBog
zElC3zodlOvT~cONCE+d+mz0sD!K_Y#E8{LHdqXARh7XsNm879jodg%fUDD`Hm4tgY
zT+*l{4d-+cTn~3ixtdDCZ5S>oCrKlDos=h}{G3Y4Q&L`%l4Ck)jF86WRnizGjY(2!
zTqlha()glE8mFXjNwOz&(gYz*+)_yslr$kp>4HvzjRWo(FWgp11xhMNQf5*oO%l@N
zl1iGSq)AE2UeZaI2<g(YO1eZzmt4|7tf-TUgjBq%l8Tg6l%)8SPMRX5Dfl0A-p>V7
zlr$wtiIPq#5mM=aN-9xONs{`?ItjKUxQ|`=p-L)KQdyGvr*#tS7;#C{b(J(tNz;-v
zFr$-Z2x;cAN}8dh8A%$vtdlMi(&Z;A=`tl<mZYI8I_U}_U3sRGu29kyNgBSYldcld
z)fJU=m6EPX(#SQPbd8X%Jy%KBDCwFcC9mtG>x6Xu6P0wGlCDcqs-lxBgj9K{k}8x`
zktBOoC(RPl?58SemXc;ADSbmH-5{hJf1;9ZP|^)a%G}gRHwo$HE0uJUl5R>;wyKk=
zgjD@gl~kpqs!JM-)pSygkZP}0QjL;ok`$lQNpplW_eLenQPP|wCFXU~JR!}ms-$^J
znwO-$1)a1&NDF_ak`^dwL6Z6xb<!dsE&jPmTBM{!NgBANlWq~xtuIv4ElRp2NrSg_
z(rrSz{iRB}O-Z*UY3Pnlx<g2JzEVkdDCv$Q4KL}WB|=(ytCE%|X-SesmUYrHAua!f
zN?N9*Wl2ij)k${=>F!^uq`Q=KSCUfqbkaRSy7yNq=^iEBlO+4TPP$J>_kXF9?o-lz
zNlHJ^Ne>9=!PhG30VO?<q|8H|^pKDqexs5eQqn_7%0ALbj|l0}uT;__N_ymyhGKP{
zR41hRw<@VlNp(qzKh{Z)3F+~7D(NvLJ(i@z6P@&gke>WnB|V{}Cz90nR3|+pq^Eza
zlAco1Q%UN7rjwo#(zCx&NzW+hnIsLY=%f`wTKQX*v_eTMk~H{SCp{;m=f6=&&nfA-
zBn`dLNiPWL#owu<7nJk@NYS0JX%;pBS2MAMA-4MB23p*=6e(=sJ8Ic4L9p$^V<GFG
zzicsl{4)D{OmB{wKZkz~n?X2khS|=LKfv8Thh4h`emKG~{)hdn2fH8tAI<ys{Gz{M
z_zcevegxq+E&hS^Wf*_&x#u1H638F<J@3xHg*9)UP52tvEB+t`-zwo8HE?eY>~pTH
z+5zYj7HQ$vR@iTjBw?d7-@}Z@$>wF)o;{tkU;_efm}Z-odm4KhP5AYZ%Ia94m@C4!
z0v!S;X_Jl6I_q8dUD(_X8?TSdLi%!FwWBd$LhYdYs~y3B<+EU;4p;+t54I6GBOiv!
z>dEXC8<qpGfT>Jj26h%D&|9fE(hzCD?beaZ&RN_*7b$e%qgYuDm18mZOq5KQpqr!R
z*f2NX5i<?AvR#g+4ftIX5D7>0p@7b#<*anxgB!W?r753Pv%(QOz>-wnoId5pH0X)<
zn)v^l;QwMxrSQhan{?2CZR}GS)LFb4#hYBPvf4kMN<%UH$8h|xp9p(`?G5-SY`3<I
znl+<lnDBI4G#24+ua7;d`wN$5+^9CV%1@$#RzolTXiQ}_F;Sd`Rdvn|!1;o$>#&E4
z_(rUjQS%f3C;nit_cbFY>`MhVrUAS+kNMgEv)>5zMp(>&(zNYX6M{TgJVV!wx?u);
k4HL_0D`%79y!#9|m3SZ}4*20fB#f^~_-_Ll_+6a;1CLN!@c;k-
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 0ce6f8fc72ee..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.type4-count",
-"tests/data/acpi/q35/DSDT.type4-count",
-"tests/data/acpi/q35/FACP.type4-count",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 05/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core count test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (3 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count Zhao Liu
` (11 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 core count
field.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.core-count | 0
tests/data/acpi/q35/DSDT.core-count | 0
tests/data/acpi/q35/FACP.core-count | 0
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.core-count
create mode 100644 tests/data/acpi/q35/DSDT.core-count
create mode 100644 tests/data/acpi/q35/FACP.core-count
diff --git a/tests/data/acpi/q35/APIC.core-count b/tests/data/acpi/q35/APIC.core-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/DSDT.core-count b/tests/data/acpi/q35/DSDT.core-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/FACP.core-count b/tests/data/acpi/q35/FACP.core-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..b9bc1961309a 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.core-count",
+"tests/data/acpi/q35/DSDT.core-count",
+"tests/data/acpi/q35/FACP.core-count",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (4 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 05/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core " Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 13:03 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 07/16] tests: bios-tables-test: Add ACPI table binaries for type4 core count test Zhao Liu
` (10 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
type4").
Test the core count field of type4 table for multiple sockets/dies case.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/qtest/bios-tables-test.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 8679255449cf..a35c753a3a00 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -999,6 +999,23 @@ static void test_acpi_q35_tcg_type4_count(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_core_count(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".core-count",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_core_count = 9,
+ .smbios_core_count2 = 9,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp 54,sockets=2,dies=3,cores=3,threads=3",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_core_count2(void)
{
test_data data = {
@@ -2166,6 +2183,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
qtest_add_func("acpi/q35/type4-count",
test_acpi_q35_tcg_type4_count);
+ qtest_add_func("acpi/q35/core-count",
+ test_acpi_q35_tcg_core_count);
qtest_add_func("acpi/q35/core-count2",
test_acpi_q35_tcg_core_count2);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 07/16] tests: bios-tables-test: Add ACPI table binaries for type4 core count test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (5 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 08/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core count2 test Zhao Liu
` (9 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.core-count | Bin 0 -> 544 bytes
tests/data/acpi/q35/DSDT.core-count | Bin 0 -> 12913 bytes
tests/data/acpi/q35/FACP.core-count | Bin 0 -> 244 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
4 files changed, 3 deletions(-)
diff --git a/tests/data/acpi/q35/APIC.core-count b/tests/data/acpi/q35/APIC.core-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d9d7ca9a896159791f6e74842d02786dc2608cb3 100644
GIT binary patch
literal 544
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z5*tHoj&S1&TM4$u*qPwwEq3p)caQxkZav`kBknxm?lbPa;QlKfyy4+H9(~~PC!Tz1
jjjVpV@0ngrUrimlY+ISr<$3?*s{?!sg0w8>S6%T3A7&l_
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/DSDT.core-count b/tests/data/acpi/q35/DSDT.core-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a24b04cbdbf09383b933a42a2a15182545543a87 100644
GIT binary patch
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HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.core-count b/tests/data/acpi/q35/FACP.core-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
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literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index b9bc1961309a..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.core-count",
-"tests/data/acpi/q35/DSDT.core-count",
-"tests/data/acpi/q35/FACP.core-count",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 08/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core count2 test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (6 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 07/16] tests: bios-tables-test: Add ACPI table binaries for type4 core count test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology Zhao Liu
` (8 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be changed about the type 4 core count2
test case.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..0f95d1344b2c 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,3 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.core-count2",
+"tests/data/acpi/q35/DSDT.core-count2",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (7 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 08/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core count2 test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 13:11 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 10/16] tests: bios-tables-test: Update ACPI table binaries for core count2 test Zhao Liu
` (7 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Currently, this case just covers the topology with only core and smt
levels, and doesn't consider more topology layers between socket and
core.
To cover the fixed case in the commit 196ea60a734c3 ("hw/smbios: Fix
core count in type4"), add the "die" level in "-smp" as the more
general topology case.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/qtest/bios-tables-test.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index a35c753a3a00..8cba1d8126f2 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1024,10 +1024,12 @@ static void test_acpi_q35_tcg_core_count2(void)
.required_struct_types = base_required_struct_types,
.required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
.smbios_core_count = 0xFF,
- .smbios_core_count2 = 275,
+ .smbios_core_count2 = 260,
};
- test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", &data);
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp 260,dies=2,cores=130,threads=1",
+ &data);
free_test_data(&data);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 10/16] tests: bios-tables-test: Update ACPI table binaries for core count2 test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (8 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 11/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count test Zhao Liu
` (6 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 3238 bytes
tests/data/acpi/q35/DSDT.core-count2 | Bin 32495 -> 33770 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 files changed, 2 deletions(-)
diff --git a/tests/data/acpi/q35/APIC.core-count2 b/tests/data/acpi/q35/APIC.core-count2
index f5da2eb1e8a93d961b39f665f2e8b02acf1aeb3c..4f2428443430b7da8321e9edd816219deb7929a2 100644
GIT binary patch
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diff --git a/tests/data/acpi/q35/DSDT.core-count2 b/tests/data/acpi/q35/DSDT.core-count2
index b47891ec10be131a59bf404242241c054ac902f8..3a0cb8c581c8cc630a2ec21712b7f8b75fcad1c8 100644
GIT binary patch
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diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 0f95d1344b2c..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.core-count2",
-"tests/data/acpi/q35/DSDT.core-count2",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 11/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (9 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 10/16] tests: bios-tables-test: Update ACPI table binaries for core count2 test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count Zhao Liu
` (5 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.thread-count | 0
tests/data/acpi/q35/DSDT.thread-count | 0
tests/data/acpi/q35/FACP.thread-count | 0
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.thread-count
create mode 100644 tests/data/acpi/q35/DSDT.thread-count
create mode 100644 tests/data/acpi/q35/FACP.thread-count
diff --git a/tests/data/acpi/q35/APIC.thread-count b/tests/data/acpi/q35/APIC.thread-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/DSDT.thread-count b/tests/data/acpi/q35/DSDT.thread-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/FACP.thread-count b/tests/data/acpi/q35/FACP.thread-count
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..4d139d7f6b7e 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.thread-count",
+"tests/data/acpi/q35/DSDT.thread-count",
+"tests/data/acpi/q35/FACP.thread-count",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (10 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 11/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 13:19 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 13/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count test Zhao Liu
` (4 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
Add this test to cover 2 cases:
1. Test thread count field with multiple sockets and multiple dies to
confirm this field could correctly calculate threads per sockets.
2. Confirm that field calculation could correctly recognize the
difference between "-smp maxcpus" and "-smp cpus".
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/qtest/bios-tables-test.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 8cba1d8126f2..26474d376633 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -95,6 +95,7 @@ typedef struct {
uint16_t smbios_cpu_curr_speed;
uint8_t smbios_core_count;
uint16_t smbios_core_count2;
+ uint8_t smbios_thread_count;
uint8_t *required_struct_types;
int required_struct_types_len;
int type4_count;
@@ -640,6 +641,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
SmbiosEntryPointType ep_type)
{
uint8_t core_count, expected_core_count = data->smbios_core_count;
+ uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
uint16_t speed, expected_speed[2];
uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
int offset[2];
@@ -663,6 +665,13 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
g_assert_cmpuint(core_count, ==, expected_core_count);
}
+ thread_count = qtest_readb(data->qts,
+ addr + offsetof(struct smbios_type_4, thread_count));
+
+ if (expected_thread_count) {
+ g_assert_cmpuint(thread_count, ==, expected_thread_count);
+ }
+
if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
core_count2 = qtest_readw(data->qts,
addr + offsetof(struct smbios_type_4, core_count2));
@@ -1033,6 +1042,22 @@ static void test_acpi_q35_tcg_core_count2(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_thread_count(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".thread-count",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_thread_count = 27,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_bridge(void)
{
test_data data = {};
@@ -2189,6 +2214,8 @@ int main(int argc, char *argv[])
test_acpi_q35_tcg_core_count);
qtest_add_func("acpi/q35/core-count2",
test_acpi_q35_tcg_core_count2);
+ qtest_add_func("acpi/q35/thread-count",
+ test_acpi_q35_tcg_thread_count);
}
qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
#ifdef CONFIG_POSIX
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 13/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (11 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 14/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count2 test Zhao Liu
` (3 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.thread-count | Bin 0 -> 544 bytes
tests/data/acpi/q35/DSDT.thread-count | Bin 0 -> 12913 bytes
tests/data/acpi/q35/FACP.thread-count | Bin 0 -> 244 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
4 files changed, 3 deletions(-)
diff --git a/tests/data/acpi/q35/APIC.thread-count b/tests/data/acpi/q35/APIC.thread-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c27e87fcf1c04a2e75f9a20f2bc6a28f19aadf66 100644
GIT binary patch
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z@i3C65UELc8x0<0IEo{wmLY`DtrcRvNOXlj!$8x-l!ca!wu6p~OCGvDdRg>y800Zs
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eg`TFbwhmpkt<321y#Mmm1<ryXDa-j)Py7K+#~uLy
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/DSDT.thread-count b/tests/data/acpi/q35/DSDT.thread-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a24b04cbdbf09383b933a42a2a15182545543a87 100644
GIT binary patch
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z!kWNl`jtm0-&}5|`y#Yk0ehvLjz#Q{jZF!7tMm+wk@{=@WoRAVtbX9An;*#smD)q>
zq7*3F=r|QkMQIB?RhfPyf1_QSqF1qX7;ols?O3~5ZeW_L&D<U3;1#n3zQs55Wr5$S
z!zg&hG8vdW)2#Zzv$Q$C(RdKDJ9Z-FL}ZcH%fDI*QyGe+XDzyCjr;2lO7!5+LpdgJ
zYvMtL>?%F1(ZhPIb+~e`R7NxEKRAT3cS19{w<0F&(KV|hI>N%+?Xh@_zjGn^s?OK$
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za-xVnJLgUKO<2U{QZi?uvF-G_iK7m^g(SKwy26Uh35(hpYF3Nxc@GJkN;*(-4}@_b
Pm7vcgZUt5Fe;xh|kQQ*J
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.thread-count b/tests/data/acpi/q35/FACP.thread-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 4d139d7f6b7e..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.thread-count",
-"tests/data/acpi/q35/DSDT.thread-count",
-"tests/data/acpi/q35/FACP.thread-count",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 14/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count2 test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (12 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 13/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2 Zhao Liu
` (2 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count2 field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.thread-count2 | 0
tests/data/acpi/q35/DSDT.thread-count2 | 0
tests/data/acpi/q35/FACP.thread-count2 | 0
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.thread-count2
create mode 100644 tests/data/acpi/q35/DSDT.thread-count2
create mode 100644 tests/data/acpi/q35/FACP.thread-count2
diff --git a/tests/data/acpi/q35/APIC.thread-count2 b/tests/data/acpi/q35/APIC.thread-count2
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/DSDT.thread-count2 b/tests/data/acpi/q35/DSDT.thread-count2
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/data/acpi/q35/FACP.thread-count2 b/tests/data/acpi/q35/FACP.thread-count2
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..d17d80e21ab9 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.thread-count2",
+"tests/data/acpi/q35/DSDT.thread-count2",
+"tests/data/acpi/q35/FACP.thread-count2",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (13 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 14/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count2 test Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-15 13:29 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 16/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count2 test Zhao Liu
2023-09-01 9:55 ` [PATCH 00/16] tests: Add CPU topology related smbios test cases Michael Tokarev
16 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
Add this test to cover 2 cases:
1. Test thread count2 field with multiple sockets and multiple dies to
confirm this field could correctly calculate threads per sockets.
2. Confirm that field calculation could correctly recognize the
difference between "-smp maxcpus" and "-smp cpus".
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/qtest/bios-tables-test.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 26474d376633..1b0c27e95d26 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -96,6 +96,7 @@ typedef struct {
uint8_t smbios_core_count;
uint16_t smbios_core_count2;
uint8_t smbios_thread_count;
+ uint16_t smbios_thread_count2;
uint8_t *required_struct_types;
int required_struct_types_len;
int type4_count;
@@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
uint16_t speed, expected_speed[2];
uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
+ uint16_t thread_count2, expected_thread_count2 = data->smbios_thread_count2;
int offset[2];
int i;
@@ -673,6 +675,8 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
}
if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
+ uint64_t thread_count2_addr;
+
core_count2 = qtest_readw(data->qts,
addr + offsetof(struct smbios_type_4, core_count2));
@@ -680,6 +684,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
if (expected_core_count == 0xFF && expected_core_count2) {
g_assert_cmpuint(core_count2, ==, expected_core_count2);
}
+
+ thread_count2_addr = addr +
+ offsetof(struct smbios_type_4, thread_count2);
+ thread_count2 = qtest_readw(data->qts, thread_count2_addr);
+
+ /* Thread Count has reached its limit, checking Thread Count 2 */
+ if (expected_thread_count == 0xFF && expected_thread_count2) {
+ g_assert_cmpuint(thread_count2, ==, expected_thread_count2);
+ }
}
}
@@ -1050,6 +1063,7 @@ static void test_acpi_q35_tcg_thread_count(void)
.required_struct_types = base_required_struct_types,
.required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
.smbios_thread_count = 27,
+ .smbios_thread_count2 = 27,
};
test_acpi_one("-machine smbios-entry-point-type=64 "
@@ -1058,6 +1072,23 @@ static void test_acpi_q35_tcg_thread_count(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_thread_count2(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".thread-count2",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_thread_count = 0xFF,
+ .smbios_thread_count2 = 260,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_bridge(void)
{
test_data data = {};
@@ -2216,6 +2247,8 @@ int main(int argc, char *argv[])
test_acpi_q35_tcg_core_count2);
qtest_add_func("acpi/q35/thread-count",
test_acpi_q35_tcg_thread_count);
+ qtest_add_func("acpi/q35/thread-count2",
+ test_acpi_q35_tcg_thread_count2);
}
qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
#ifdef CONFIG_POSIX
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 16/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count2 test
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (14 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2 Zhao Liu
@ 2023-08-25 3:36 ` Zhao Liu
2023-09-01 9:55 ` [PATCH 00/16] tests: Add CPU topology related smbios test cases Michael Tokarev
16 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-08-25 3:36 UTC (permalink / raw)
To: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel
Cc: Michael Tokarev, Zhenyu Wang, Zhao Liu
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WOA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-UMA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00001CE6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : CA
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[1C8Ch 7308 1] Subtable Type : 09 [Processor Local x2APIC]
+[1C8Dh 7309 1] Length : 10
+[1C8Eh 7310 2] Reserved : 0000
+[1C90h 7312 4] Processor x2Apic ID : 00000381
+[1C94h 7316 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[1C98h 7320 4] Processor UID : 00000207
+
+[1C9Ch 7324 1] Subtable Type : 01 [I/O APIC]
+[1C9Dh 7325 1] Length : 0C
+[1C9Eh 7326 1] I/O Apic ID : 00
+[1C9Fh 7327 1] Reserved : 00
+[1CA0h 7328 4] Address : FEC00000
+[1CA4h 7332 4] Interrupt : 00000000
+
+[1CA8h 7336 1] Subtable Type : 02 [Interrupt Source Override]
+[1CA9h 7337 1] Length : 0A
+[1CAAh 7338 1] Bus : 00
+[1CABh 7339 1] Source : 00
+[1CACh 7340 4] Interrupt : 00000002
+[1CB0h 7344 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1CB2h 7346 1] Subtable Type : 02 [Interrupt Source Override]
+[1CB3h 7347 1] Length : 0A
+[1CB4h 7348 1] Bus : 00
+[1CB5h 7349 1] Source : 05
+[1CB6h 7350 4] Interrupt : 00000005
+[1CBAh 7354 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CBCh 7356 1] Subtable Type : 02 [Interrupt Source Override]
+[1CBDh 7357 1] Length : 0A
+[1CBEh 7358 1] Bus : 00
+[1CBFh 7359 1] Source : 09
+[1CC0h 7360 4] Interrupt : 00000009
+[1CC4h 7364 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CC6h 7366 1] Subtable Type : 02 [Interrupt Source Override]
+[1CC7h 7367 1] Length : 0A
+[1CC8h 7368 1] Bus : 00
+[1CC9h 7369 1] Source : 0A
+[1CCAh 7370 4] Interrupt : 0000000A
+[1CCEh 7374 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CD0h 7376 1] Subtable Type : 02 [Interrupt Source Override]
+[1CD1h 7377 1] Length : 0A
+[1CD2h 7378 1] Bus : 00
+[1CD3h 7379 1] Source : 0B
+[1CD4h 7380 4] Interrupt : 0000000B
+[1CD8h 7384 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CDAh 7386 1] Subtable Type : 0A [Local x2APIC NMI]
+[1CDBh 7387 1] Length : 0C
+[1CDCh 7388 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[1CDEh 7390 4] Processor UID : FFFFFFFF
+[1CE2h 7394 1] Interrupt Input LINT : 01
+[1CE3h 7395 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-LWJ191, Wed Aug 23 22:29:53 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000F8B7 (63671)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xB7
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/data/acpi/q35/APIC.thread-count2 | Bin 0 -> 7398 bytes
tests/data/acpi/q35/DSDT.thread-count2 | Bin 0 -> 63671 bytes
tests/data/acpi/q35/FACP.thread-count2 | Bin 0 -> 244 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
4 files changed, 3 deletions(-)
diff --git a/tests/data/acpi/q35/APIC.thread-count2 b/tests/data/acpi/q35/APIC.thread-count2
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..2c6ab5d96c275f8e4872ff91ce3006f992ef3c36 100644
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diff --git a/tests/data/acpi/q35/DSDT.thread-count2 b/tests/data/acpi/q35/DSDT.thread-count2
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HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.thread-count2 b/tests/data/acpi/q35/FACP.thread-count2
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index d17d80e21ab9..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.thread-count2",
-"tests/data/acpi/q35/DSDT.thread-count2",
-"tests/data/acpi/q35/FACP.thread-count2",
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
` (15 preceding siblings ...)
2023-08-25 3:36 ` [PATCH 16/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count2 test Zhao Liu
@ 2023-09-01 9:55 ` Michael Tokarev
2023-09-05 6:56 ` Zhao Liu
2023-09-06 14:40 ` Philippe Mathieu-Daudé
16 siblings, 2 replies; 38+ messages in thread
From: Michael Tokarev @ 2023-09-01 9:55 UTC (permalink / raw)
To: Zhao Liu, Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Eduardo Habkost, Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, qemu-devel
Cc: Zhenyu Wang, Zhao Liu
25.08.2023 06:36, Zhao Liu wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> Hi all,
>
> This patchset is the follow up tests of previous topology fixes in
> smbios [1].
>
> In this patchset, add these test cases:
>
> 1. Add the case to test 2 newly added topology helpers (patch 1):
> * machine_topo_get_cores_per_socket()
> * machine_topo_get_threads_per_socket()
>
> 2. Add the cases in bios-tables-test.c to:
> * test smbios type4 table count (patch 2-4).
> * test smbios type4 core count field (patch 5-7).
> * update the test of smbios type4 core count2 field (patch 8-10).
> * test smbios type4 thread count (patch 11-13).
> * test smbios type4 thread count2 (patch 14-16).
>
> With the above new cases, cover all commits of [1] in test.
>
> [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
Hmm. I definitely didn't expect such a large patchset.. I asked for just
a small, maybe manual (from command-line) reproducer of the original issue,
so I can verify it is fixed before applying the change in question to qemu
stable trees. It is a large work. Lemme at least give it a try in the
gitlab CI...
Philippe, can you pick this up for the misc tree?
/mjt
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
2023-09-01 9:55 ` [PATCH 00/16] tests: Add CPU topology related smbios test cases Michael Tokarev
@ 2023-09-05 6:56 ` Zhao Liu
2023-09-15 13:48 ` Michael S. Tsirkin
2023-09-06 14:40 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-09-05 6:56 UTC (permalink / raw)
To: Michael Tokarev
Cc: Michael S . Tsirkin, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel, Zhenyu Wang, Zhao Liu
Hi Michael,
On Fri, Sep 01, 2023 at 12:55:33PM +0300, Michael Tokarev wrote:
> Date: Fri, 1 Sep 2023 12:55:33 +0300
> From: Michael Tokarev <mjt@tls.msk.ru>
> Subject: Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
>
> 25.08.2023 06:36, Zhao Liu wrote:
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > Hi all,
> >
> > This patchset is the follow up tests of previous topology fixes in
> > smbios [1].
> >
> > In this patchset, add these test cases:
> >
> > 1. Add the case to test 2 newly added topology helpers (patch 1):
> > * machine_topo_get_cores_per_socket()
> > * machine_topo_get_threads_per_socket()
> >
> > 2. Add the cases in bios-tables-test.c to:
> > * test smbios type4 table count (patch 2-4).
> > * test smbios type4 core count field (patch 5-7).
> > * update the test of smbios type4 core count2 field (patch 8-10).
> > * test smbios type4 thread count (patch 11-13).
> > * test smbios type4 thread count2 (patch 14-16).
> >
> > With the above new cases, cover all commits of [1] in test.
> >
> > [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
>
> Hmm. I definitely didn't expect such a large patchset.. I asked for just
> a small, maybe manual (from command-line) reproducer of the original issue,
> so I can verify it is fixed before applying the change in question to qemu
> stable trees.
Since these issues are found by coding reading, they are "byproducts" of
other topology-related work I've been woring on, not directly identified
by any anomaly...
...So I'm not quite sure what the consequences of these few misuses of
topology fields are, and how they might manifest themselves.
> It is a large work. Lemme at least give it a try in the
> gitlab CI...
The test cases are the ones that clearly define the relevant topology
issues.
Thanks,
Zhao
>
> Philippe, can you pick this up for the misc tree?
>
> /mjt
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
2023-09-01 9:55 ` [PATCH 00/16] tests: Add CPU topology related smbios test cases Michael Tokarev
2023-09-05 6:56 ` Zhao Liu
@ 2023-09-06 14:40 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-09-06 14:40 UTC (permalink / raw)
To: Michael Tokarev, Zhao Liu, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Eduardo Habkost, Marcel Apfelbaum, Yanan Wang,
qemu-devel
Cc: Zhenyu Wang, Zhao Liu
On 1/9/23 11:55, Michael Tokarev wrote:
> 25.08.2023 06:36, Zhao Liu wrote:
>> From: Zhao Liu <zhao1.liu@intel.com>
>>
>> Hi all,
>>
>> This patchset is the follow up tests of previous topology fixes in
>> smbios [1].
>>
>> In this patchset, add these test cases:
>>
>> 1. Add the case to test 2 newly added topology helpers (patch 1):
>> * machine_topo_get_cores_per_socket()
>> * machine_topo_get_threads_per_socket()
>>
>> 2. Add the cases in bios-tables-test.c to:
>> * test smbios type4 table count (patch 2-4).
>> * test smbios type4 core count field (patch 5-7).
>> * update the test of smbios type4 core count2 field (patch 8-10).
>> * test smbios type4 thread count (patch 11-13).
>> * test smbios type4 thread count2 (patch 14-16).
>>
>> With the above new cases, cover all commits of [1] in test.
>>
>> [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
>
> Hmm. I definitely didn't expect such a large patchset.. I asked for just
> a small, maybe manual (from command-line) reproducer of the original issue,
> so I can verify it is fixed before applying the change in question to qemu
> stable trees. It is a large work. Lemme at least give it a try in the
> gitlab CI...
>
> Philippe, can you pick this up for the misc tree?
This area have well defined maintainers:
$ ./scripts/get_maintainer.pl -f tests/data/acpi/
"Michael S. Tsirkin" <mst@redhat.com> (supporter:ACPI/SMBIOS)
Igor Mammedov <imammedo@redhat.com> (supporter:ACPI/SMBIOS)
Ani Sinha <anisinha@redhat.com> (reviewer:ACPI/SMBIOS)
So I'll pass ;)
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers
2023-08-25 3:36 ` [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers Zhao Liu
@ 2023-09-15 12:31 ` Igor Mammedov
2023-09-19 7:18 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 12:31 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:04 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> Use the different ways to calculate cores/threads per socket, so that
> the new CPU topology levels won't be missed in these 2 helpes:
>
> * machine_topo_get_cores_per_socket()
> * machine_topo_get_threads_per_socket()
>
> Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
> threads per socket").
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
> tests/unit/test-smp-parse.c | 67 ++++++++++++++++++++++++++++++-------
> 1 file changed, 54 insertions(+), 13 deletions(-)
>
> diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
> index fdc39a846ca6..24972666a74d 100644
> --- a/tests/unit/test-smp-parse.c
> +++ b/tests/unit/test-smp-parse.c
> @@ -394,20 +394,47 @@ static char *smp_config_to_string(const SMPConfiguration *config)
> config->has_maxcpus ? "true" : "false", config->maxcpus);
> }
>
> -static char *cpu_topology_to_string(const CpuTopology *topo)
> +/* Use the different calculation than machine_topo_get_threads_per_socket(). */
> +static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo)
> +{
> + /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
> + if (!topo->sockets) {
> + return 0;
> + } else {
> + return topo->max_cpus / topo->sockets;
> + }
> +}
> +
> +/* Use the different calculation than machine_topo_get_cores_per_socket(). */
> +static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo)
> +{
> + /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
> + if (!topo->threads) {
> + return 0;
> + } else {
> + return cpu_topology_get_threads_per_socket(topo) / topo->threads;
> + }
> +}
> +
> +static char *cpu_topology_to_string(const CpuTopology *topo,
> + unsigned int threads_per_socket,
> + unsigned int cores_per_socket)
> {
> return g_strdup_printf(
> "(CpuTopology) {\n"
> - " .cpus = %u,\n"
> - " .sockets = %u,\n"
> - " .dies = %u,\n"
> - " .clusters = %u,\n"
> - " .cores = %u,\n"
> - " .threads = %u,\n"
> - " .max_cpus = %u,\n"
> + " .cpus = %u,\n"
> + " .sockets = %u,\n"
> + " .dies = %u,\n"
> + " .clusters = %u,\n"
> + " .cores = %u,\n"
> + " .threads = %u,\n"
> + " .max_cpus = %u,\n"
> + " .threads_per_socket = %u,\n"
> + " .cores_per_socket = %u,\n"
> "}",
> topo->cpus, topo->sockets, topo->dies, topo->clusters,
> - topo->cores, topo->threads, topo->max_cpus);
> + topo->cores, topo->threads, topo->max_cpus,
> + threads_per_socket, cores_per_socket);
> }
>
> static void check_parse(MachineState *ms, const SMPConfiguration *config,
> @@ -415,14 +442,26 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
> bool is_valid)
> {
> g_autofree char *config_str = smp_config_to_string(config);
> - g_autofree char *expect_topo_str = cpu_topology_to_string(expect_topo);
> - g_autofree char *output_topo_str = NULL;
> + g_autofree char *expect_topo_str = NULL, *output_topo_str = NULL;
> + unsigned int expect_threads_per_socket, expect_cores_per_socket;
> + unsigned int ms_threads_per_socket, ms_cores_per_socket;
> Error *err = NULL;
>
> + expect_threads_per_socket =
> + cpu_topology_get_threads_per_socket(expect_topo);
> + expect_cores_per_socket =
> + cpu_topology_get_cores_per_socket(expect_topo);
> + expect_topo_str = cpu_topology_to_string(expect_topo,
> + expect_threads_per_socket,
> + expect_cores_per_socket);
> +
> /* call the generic parser */
> machine_parse_smp_config(ms, config, &err);
>
> - output_topo_str = cpu_topology_to_string(&ms->smp);
> + ms_threads_per_socket = machine_topo_get_threads_per_socket(ms);
> + ms_cores_per_socket = machine_topo_get_cores_per_socket(ms);
> + output_topo_str = cpu_topology_to_string(&ms->smp, ms_threads_per_socket,
> + ms_cores_per_socket);
>
> /* when the configuration is supposed to be valid */
> if (is_valid) {
> @@ -433,7 +472,9 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
> (ms->smp.clusters == expect_topo->clusters) &&
> (ms->smp.cores == expect_topo->cores) &&
> (ms->smp.threads == expect_topo->threads) &&
> - (ms->smp.max_cpus == expect_topo->max_cpus)) {
> + (ms->smp.max_cpus == expect_topo->max_cpus) &&
> + (ms_threads_per_socket == expect_threads_per_socket) &&
> + (ms_cores_per_socket == expect_cores_per_socket)) {
> return;
> }
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count
2023-08-25 3:36 ` [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count Zhao Liu
@ 2023-09-15 12:54 ` Igor Mammedov
2023-09-19 7:20 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 12:54 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:06 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
> calculation").
>
> Test the count of type4 tables for multiple sockets case.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> tests/qtest/bios-tables-test.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 47ba20b9579b..8679255449cf 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -97,6 +97,7 @@ typedef struct {
> uint16_t smbios_core_count2;
> uint8_t *required_struct_types;
> int required_struct_types_len;
> + int type4_count;
> QTestState *qts;
> } test_data;
>
> @@ -673,12 +674,21 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> }
> }
>
> +static void smbios_type4_count_test(test_data *data, int type4_count)
> +{
> + int expected_type4_count = data->type4_count;
> +
> + if (expected_type4_count) {
> + g_assert_cmpuint(type4_count, ==, expected_type4_count);
> + }
> +}
> +
> static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
> {
> DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
>
> SmbiosEntryPoint *ep_table = &data->smbios_ep_table;
> - int i = 0, len, max_len = 0;
> + int i = 0, len, max_len = 0, type4_count = 0;
> uint8_t type, prv, crt;
> uint64_t addr;
>
> @@ -704,6 +714,7 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
>
> if (type == 4) {
> smbios_cpu_test(data, addr, ep_type);
> + type4_count++;
> }
>
> /* seek to end of unformatted string area of this struct ("\0\0") */
> @@ -747,6 +758,8 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
> for (i = 0; i < data->required_struct_types_len; i++) {
> g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
> }
> +
> + smbios_type4_count_test(data, type4_count);
> }
>
> static void test_acpi_load_tables(test_data *data)
> @@ -970,6 +983,22 @@ static void test_acpi_q35_tcg(void)
> free_test_data(&data);
> }
>
> +static void test_acpi_q35_tcg_type4_count(void)
> +{
> + test_data data = {
> + .machine = MACHINE_Q35,
> + .variant = ".type4-count",
> + .required_struct_types = base_required_struct_types,
> + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> + .type4_count = 5,
> + };
> +
> + test_acpi_one("-machine smbios-entry-point-type=64 "
> + "-smp cpus=100,maxcpus=120,sockets=5,"
> + "dies=2,cores=4,threads=3", &data);
I'd add to commit message an explanation why above topology was picked up
> + free_test_data(&data);
> +}
> +
> static void test_acpi_q35_tcg_core_count2(void)
> {
> test_data data = {
> @@ -2135,6 +2164,8 @@ int main(int argc, char *argv[])
> if (has_kvm) {
> qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
> qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
> + qtest_add_func("acpi/q35/type4-count",
> + test_acpi_q35_tcg_type4_count);
> qtest_add_func("acpi/q35/core-count2",
> test_acpi_q35_tcg_core_count2);
> }
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count
2023-08-25 3:36 ` [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count Zhao Liu
@ 2023-09-15 13:03 ` Igor Mammedov
2023-09-19 7:21 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 13:03 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:09 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
> type4").
>
> Test the core count field of type4 table for multiple sockets/dies case.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> tests/qtest/bios-tables-test.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 8679255449cf..a35c753a3a00 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -999,6 +999,23 @@ static void test_acpi_q35_tcg_type4_count(void)
> free_test_data(&data);
> }
>
> +static void test_acpi_q35_tcg_core_count(void)
> +{
> + test_data data = {
> + .machine = MACHINE_Q35,
> + .variant = ".core-count",
> + .required_struct_types = base_required_struct_types,
> + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> + .smbios_core_count = 9,
> + .smbios_core_count2 = 9,
> + };
> +
> + test_acpi_one("-machine smbios-entry-point-type=64 "
> + "-smp 54,sockets=2,dies=3,cores=3,threads=3",
ditto as for 3/16
It's not obvious why this topology is used and how it correlates to smbios_core_*
so describe setup in commit message
> + &data);
> + free_test_data(&data);
> +}
> +
> static void test_acpi_q35_tcg_core_count2(void)
> {
> test_data data = {
> @@ -2166,6 +2183,8 @@ int main(int argc, char *argv[])
> qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
> qtest_add_func("acpi/q35/type4-count",
> test_acpi_q35_tcg_type4_count);
> + qtest_add_func("acpi/q35/core-count",
> + test_acpi_q35_tcg_core_count);
> qtest_add_func("acpi/q35/core-count2",
> test_acpi_q35_tcg_core_count2);
> }
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test
2023-08-25 3:36 ` [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test Zhao Liu
@ 2023-09-15 13:05 ` Igor Mammedov
2023-09-19 7:26 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 13:05 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:07 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
copy/past mistake in subj?
shouldn't it be for 'smbios type4 count'?
> From: Zhao Liu <zhao1.liu@intel.com>
>
> Following the guidelines in tests/qtest/bios-tables-test.c, this
> is step 5 and 6.
>
> Changes in the tables:
> FACP:
>
> +/*
> + * Intel ACPI Component Architecture
> + * AML/ASL+ Disassembler version 20200925 (64-bit version)
> + * Copyright (c) 2000 - 2020 Intel Corporation
> + *
> + * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
> + *
> + * ACPI Data Table [FACP]
> + *
> + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
> + */
> +
> +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
> +[004h 0004 4] Table Length : 000000F4
> +[008h 0008 1] Revision : 03
> +[009h 0009 1] Checksum : B3
> +[00Ah 0010 6] Oem ID : "BOCHS "
> +[010h 0016 8] Oem Table ID : "BXPC "
> +[018h 0024 4] Oem Revision : 00000001
> +[01Ch 0028 4] Asl Compiler ID : "BXPC"
> +[020h 0032 4] Asl Compiler Revision : 00000001
> +
> +[024h 0036 4] FACS Address : 00000000
> +[028h 0040 4] DSDT Address : 00000000
> +[02Ch 0044 1] Model : 01
> +[02Dh 0045 1] PM Profile : 00 [Unspecified]
> +[02Eh 0046 2] SCI Interrupt : 0009
> +[030h 0048 4] SMI Command Port : 000000B2
> +[034h 0052 1] ACPI Enable Value : 02
> +[035h 0053 1] ACPI Disable Value : 03
> +[036h 0054 1] S4BIOS Command : 00
> +[037h 0055 1] P-State Control : 00
> +[038h 0056 4] PM1A Event Block Address : 00000600
> +[03Ch 0060 4] PM1B Event Block Address : 00000000
> +[040h 0064 4] PM1A Control Block Address : 00000604
> +[044h 0068 4] PM1B Control Block Address : 00000000
> +[048h 0072 4] PM2 Control Block Address : 00000000
> +[04Ch 0076 4] PM Timer Block Address : 00000608
> +[050h 0080 4] GPE0 Block Address : 00000620
> +[054h 0084 4] GPE1 Block Address : 00000000
> +[058h 0088 1] PM1 Event Block Length : 04
> +[059h 0089 1] PM1 Control Block Length : 02
> +[05Ah 0090 1] PM2 Control Block Length : 00
> +[05Bh 0091 1] PM Timer Block Length : 04
> +[05Ch 0092 1] GPE0 Block Length : 10
> +[05Dh 0093 1] GPE1 Block Length : 00
> +[05Eh 0094 1] GPE1 Base Offset : 00
> +[05Fh 0095 1] _CST Support : 00
> +[060h 0096 2] C2 Latency : 0FFF
> +[062h 0098 2] C3 Latency : 0FFF
> +[064h 0100 2] CPU Cache Size : 0000
> +[066h 0102 2] Cache Flush Stride : 0000
> +[068h 0104 1] Duty Cycle Offset : 00
> +[069h 0105 1] Duty Cycle Width : 00
> +[06Ah 0106 1] RTC Day Alarm Index : 00
> +[06Bh 0107 1] RTC Month Alarm Index : 00
> +[06Ch 0108 1] RTC Century Index : 32
> +[06Dh 0109 2] Boot Flags (decoded below) : 0002
> + Legacy Devices Supported (V2) : 0
> + 8042 Present on ports 60/64 (V2) : 1
> + VGA Not Present (V4) : 0
> + MSI Not Supported (V4) : 0
> + PCIe ASPM Not Supported (V4) : 0
> + CMOS RTC Not Present (V5) : 0
> +[06Fh 0111 1] Reserved : 00
> +[070h 0112 4] Flags (decoded below) : 000484A5
> + WBINVD instruction is operational (V1) : 1
> + WBINVD flushes all caches (V1) : 0
> + All CPUs support C1 (V1) : 1
> + C2 works on MP system (V1) : 0
> + Control Method Power Button (V1) : 0
> + Control Method Sleep Button (V1) : 1
> + RTC wake not in fixed reg space (V1) : 0
> + RTC can wake system from S4 (V1) : 1
> + 32-bit PM Timer (V1) : 0
> + Docking Supported (V1) : 0
> + Reset Register Supported (V2) : 1
> + Sealed Case (V3) : 0
> + Headless - No Video (V3) : 0
> + Use native instr after SLP_TYPx (V3) : 0
> + PCIEXP_WAK Bits Supported (V4) : 0
> + Use Platform Timer (V4) : 1
> + RTC_STS valid on S4 wake (V4) : 0
> + Remote Power-on capable (V4) : 0
> + Use APIC Cluster Model (V4) : 1
> + Use APIC Physical Destination Mode (V4) : 0
> + Hardware Reduced (V5) : 0
> + Low Power S0 Idle (V5) : 0
> +
> +[074h 0116 12] Reset Register : [Generic Address Structure]
> +[074h 0116 1] Space ID : 01 [SystemIO]
> +[075h 0117 1] Bit Width : 08
> +[076h 0118 1] Bit Offset : 00
> +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[078h 0120 8] Address : 0000000000000CF9
> +
> +[080h 0128 1] Value to cause reset : 0F
> +[081h 0129 2] ARM Flags (decoded below) : 0000
> + PSCI Compliant : 0
> + Must use HVC for PSCI : 0
> +
> +[083h 0131 1] FADT Minor Revision : 00
> +[084h 0132 8] FACS Address : 0000000000000000
> +[08Ch 0140 8] DSDT Address : 0000000000000000
> +[094h 0148 12] PM1A Event Block : [Generic Address Structure]
> +[094h 0148 1] Space ID : 01 [SystemIO]
> +[095h 0149 1] Bit Width : 20
> +[096h 0150 1] Bit Offset : 00
> +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[098h 0152 8] Address : 0000000000000600
> +
> +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
> +[0A0h 0160 1] Space ID : 00 [SystemMemory]
> +[0A1h 0161 1] Bit Width : 00
> +[0A2h 0162 1] Bit Offset : 00
> +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0A4h 0164 8] Address : 0000000000000000
> +
> +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
> +[0ACh 0172 1] Space ID : 01 [SystemIO]
> +[0ADh 0173 1] Bit Width : 10
> +[0AEh 0174 1] Bit Offset : 00
> +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0B0h 0176 8] Address : 0000000000000604
> +
> +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
> +[0B8h 0184 1] Space ID : 00 [SystemMemory]
> +[0B9h 0185 1] Bit Width : 00
> +[0BAh 0186 1] Bit Offset : 00
> +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0BCh 0188 8] Address : 0000000000000000
> +
> +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
> +[0C4h 0196 1] Space ID : 00 [SystemMemory]
> +[0C5h 0197 1] Bit Width : 00
> +[0C6h 0198 1] Bit Offset : 00
> +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0C8h 0200 8] Address : 0000000000000000
> +
> +[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
> +[0D0h 0208 1] Space ID : 01 [SystemIO]
> +[0D1h 0209 1] Bit Width : 20
> +[0D2h 0210 1] Bit Offset : 00
> +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0D4h 0212 8] Address : 0000000000000608
> +
> +[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
> +[0DCh 0220 1] Space ID : 01 [SystemIO]
> +[0DDh 0221 1] Bit Width : 80
> +[0DEh 0222 1] Bit Offset : 00
> +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0E0h 0224 8] Address : 0000000000000620
> +
> +[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
> +[0E8h 0232 1] Space ID : 00 [SystemMemory]
> +[0E9h 0233 1] Bit Width : 00
> +[0EAh 0234 1] Bit Offset : 00
> +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
> +[0ECh 0236 8] Address : 0000000000000000
> +
> ...
>
> APIC:
>
> +/*
> + * Intel ACPI Component Architecture
> + * AML/ASL+ Disassembler version 20200925 (64-bit version)
> + * Copyright (c) 2000 - 2020 Intel Corporation
> + *
> + * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
> + *
> + * ACPI Data Table [APIC]
> + *
> + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
> + */
> +
> +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
> +[004h 0004 4] Table Length : 00000430
> +[008h 0008 1] Revision : 03
> +[009h 0009 1] Checksum : C5
> +[00Ah 0010 6] Oem ID : "BOCHS "
> +[010h 0016 8] Oem Table ID : "BXPC "
> +[018h 0024 4] Oem Revision : 00000001
> +[01Ch 0028 4] Asl Compiler ID : "BXPC"
> +[020h 0032 4] Asl Compiler Revision : 00000001
> +
> +[024h 0036 4] Local Apic Address : FEE00000
> +[028h 0040 4] Flags (decoded below) : 00000001
> + PC-AT Compatibility : 1
> +
> +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
> +[02Dh 0045 1] Length : 08
> +[02Eh 0046 1] Processor ID : 00
> +[02Fh 0047 1] Local Apic ID : 00
> +[030h 0048 4] Flags (decoded below) : 00000001
> + Processor Enabled : 1
> + Runtime Online Capable : 0
> +
> +[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
> +[035h 0053 1] Length : 08
> +[036h 0054 1] Processor ID : 01
> +[037h 0055 1] Local Apic ID : 01
> +[038h 0056 4] Flags (decoded below) : 00000001
> + Processor Enabled : 1
> + Runtime Online Capable : 0
>
> [snip]
>
> +[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
> +[3E5h 0997 1] Length : 08
> +[3E6h 0998 1] Processor ID : 77
> +[3E7h 0999 1] Local Apic ID : 9E
> +[3E8h 1000 4] Flags (decoded below) : 00000000
> + Processor Enabled : 0
> + Runtime Online Capable : 0
> +
> +[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
> +[3EDh 1005 1] Length : 0C
> +[3EEh 1006 1] I/O Apic ID : 00
> +[3EFh 1007 1] Reserved : 00
> +[3F0h 1008 4] Address : FEC00000
> +[3F4h 1012 4] Interrupt : 00000000
> +
> +[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
> +[3F9h 1017 1] Length : 0A
> +[3FAh 1018 1] Bus : 00
> +[3FBh 1019 1] Source : 00
> +[3FCh 1020 4] Interrupt : 00000002
> +[400h 1024 2] Flags (decoded below) : 0000
> + Polarity : 0
> + Trigger Mode : 0
> +
> +[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
> +[403h 1027 1] Length : 0A
> +[404h 1028 1] Bus : 00
> +[405h 1029 1] Source : 05
> +[406h 1030 4] Interrupt : 00000005
> +[40Ah 1034 2] Flags (decoded below) : 000D
> + Polarity : 1
> + Trigger Mode : 3
> +
> +[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
> +[40Dh 1037 1] Length : 0A
> +[40Eh 1038 1] Bus : 00
> +[40Fh 1039 1] Source : 09
> +[410h 1040 4] Interrupt : 00000009
> +[414h 1044 2] Flags (decoded below) : 000D
> + Polarity : 1
> + Trigger Mode : 3
> +
> +[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
> +[417h 1047 1] Length : 0A
> +[418h 1048 1] Bus : 00
> +[419h 1049 1] Source : 0A
> +[41Ah 1050 4] Interrupt : 0000000A
> +[41Eh 1054 2] Flags (decoded below) : 000D
> + Polarity : 1
> + Trigger Mode : 3
> +
> +[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
> +[421h 1057 1] Length : 0A
> +[422h 1058 1] Bus : 00
> +[423h 1059 1] Source : 0B
> +[424h 1060 4] Interrupt : 0000000B
> +[428h 1064 2] Flags (decoded below) : 000D
> + Polarity : 1
> + Trigger Mode : 3
> +
> +[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
> +[42Bh 1067 1] Length : 06
> +[42Ch 1068 1] Processor ID : FF
> +[42Dh 1069 2] Flags (decoded below) : 0000
> + Polarity : 0
> + Trigger Mode : 0
> +[42Fh 1071 1] Interrupt Input LINT : 01
> +
> ...
>
> DSDT:
>
> +/*
> + * Intel ACPI Component Architecture
> + * AML/ASL+ Disassembler version 20200925 (64-bit version)
> + * Copyright (c) 2000 - 2020 Intel Corporation
> + *
> + * Disassembling to symbolic ASL+ operators
> + *
> + * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
> + *
> + * Original Table Header:
> + * Signature "DSDT"
> + * Length 0x0000489D (18589)
> + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
> + * Checksum 0xDB
> + * OEM ID "BOCHS "
> + * OEM Table ID "BXPC "
> + * OEM Revision 0x00000001 (1)
> + * Compiler ID "BXPC"
> + * Compiler Version 0x00000001 (1)
> + */
> +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
> +{
> + Scope (\)
> + {
> + OperationRegion (DBG, SystemIO, 0x0402, One)
> + Field (DBG, ByteAcc, NoLock, Preserve)
> + {
> + DBGB, 8
> + }
> +
> + Method (DBUG, 1, NotSerialized)
> + {
> + ToHexString (Arg0, Local0)
> + ToBuffer (Local0, Local0)
> + Local1 = (SizeOf (Local0) - One)
> + Local2 = Zero
> + While ((Local2 < Local1))
> + {
> + DBGB = DerefOf (Local0 [Local2])
> + Local2++
> + }
> +
> + DBGB = 0x0A
> + }
> + }
> +
>
> [snip]
>
> +
> + Processor (C000, 0x00, 0x00000000, 0x00)
> + {
> + Method (_STA, 0, Serialized) // _STA: Status
> + {
> + Return (CSTA (Zero))
> + }
> +
> + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
> + {
> + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
> + })
> + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
> + {
> + COST (Zero, Arg0, Arg1, Arg2)
> + }
> + }
> +
> + Processor (C001, 0x01, 0x00000000, 0x00)
> + {
> + Method (_STA, 0, Serialized) // _STA: Status
> + {
> + Return (CSTA (One))
> + }
> +
> + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
> + {
> + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
> + })
> + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
> + {
> + CEJ0 (One)
> + }
> +
> + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
> + {
> + COST (One, Arg0, Arg1, Arg2)
> + }
> + }
>
> [snip]
>
> + Processor (C077, 0x77, 0x00000000, 0x00)
> + {
> + Method (_STA, 0, Serialized) // _STA: Status
> + {
> + Return (CSTA (0x77))
> + }
> +
> + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
> + {
> + 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w.....
> + })
> + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
> + {
> + CEJ0 (0x77)
> + }
> +
> + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
> + {
> + COST (0x77, Arg0, Arg1, Arg2)
> + }
> + }
> + }
> + }
> +
> ...
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
> tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
> tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
> tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
> 4 files changed, 3 deletions(-)
>
> diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count
> index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ab60a6ef065d8ce53ae93d311d3777d2d4afb9f6 100644
> GIT binary patch
> literal 1072
> zcmXxjX)mKu7{>9_YU}A{8~a-OZpzsAwwBgf>(n~-!C>rL5ClOG1VQjwyzxDJ5<E};
> zagzJ~UFYQFB<IC#bGsZ?jSxO>_Ev|p!(#Wi9Ts`1gb+$r6yp8Et0V-fRH#;?j|Meb
> z)ap<tp|2h#1L{p^Fr(2AO#x^QM86>P55|BH3=GAfaQqR0!I2mejiE6Z7K`EDe+elf
> zo_%BjMkQf%GRCA}Y#PR;qa_35voIkW6LT=hipjZ{l834Jm{x%4g_u!{nI)K2irM9u
> zQ-MD#(OQkUHq5i*uNus+#ezC4bYhVUiyN?{2}_%?tOd*6SkZ=+?O4@`)m>=oM!N?c
> zJy_F=wf$H(fc1mu975MHHjH577&eV#^8~g`V(S#Tr?G7Y+h?(34m;<uYXQ3#@%J)%
> zR<LIkd)KjV1N%2|U<(Jg@y`wp?c(qrj_l*;0gfGd$3+@H!ii)2dxDdvICX~8=lJge
> zXD)H}3g@oz{|(OH;=&y+-s92(E<fVR6Rtkv+KZyfr1aMhrK=5cDM3kEt*lu|di{4Y
> Q$QL*>8of!Q`;?#f0%hq@0RR91
>
> literal 0
> HcmV?d00001
>
> diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count
> index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..edc23198cdb47a981bcbc82bc8e392b815abb554 100644
> GIT binary patch
> literal 18589
> zcmb81No*V0c804+N}`ICL`n1{%eE}fGfB;!$s#FI5@m{%JW)2O!M5a)9%Q$><G@xY
> z{kn}Lc-?y4cnR_XbwdxxE&&2$nHb0>+4U|Byj2$2yloJ?UOnfWdvDb}b*~J>UQquj
> zp7Wh^io+pqT{B%yPyZ%o80PO%m+V}*Cv~-G_rO2XFbvfAH<Ay`8kN`S)M(WV`2uF;
> zO^9i@Nd=?F)2W$J^VdtY?`pMYzo?mWbz}aA$hY%z_0PYo%^T>nGGDhW6p``HYB^P{
> ztmfN_c0LxY=JM%q@<%HetlC`pgVmXQ+K5gxRWFt8z}tI<oxT!ZpKMrLYVWinmBR1(
> z{;;R};&)e`CEuO<&)aYBSpjfJz~3PJ?W^NW?X#M-yS5(rW^LJgh2iYJ_<H9zYwT`*
> zEQ0scYk1`QFh7K-_{P2Hcta*#F0`x<uH7~2?S9j!t#^IH3;1#9KmNNs@M+=eZND$<
> z_&2+-QCn~NcG>c6)auroFKdPY2fEkpT21wi2A|Pl)Zi@KH;lRZ9KW-&I-D*gZPs~9
> zak3b*V{rqzFO}Q(Slz$aW*A{S<@oO(-@kwVuUs0DmquhFdJ<0_p18{EqFtUgL+`>?
> zu<|B?h7HGOdf+DAQ+Zv^jKM?o?_nzdj};nrDwY|8J5rN{k{SAuhoNDoCT9vg#eDi|
> zPsL14*yBd@K+(>O`6~O+djGz@gdX*m=CXl|${{?wVMLE5A!ai#WYzJeCVXqrRCAG?
> z&vfHQolrPyn1r1`xG{}+co<%-%^Pd;VK_JMjaPH#+^e~lrqv`*@cIGI*;fGddHyg2
> zi+MY1M8j41Yu1<0imYBX@%%>Y-?Qgtu{2%m7=QY@BNPZhu8GO<jKQ@DI%{-<@wnv!
> zW7IMHVC0OBmH^ZT4<q*z7Dj<%E5DD$fvaO;B=DK9k41v7urShb^%*P@Tv;TT7zx!d
> zUq6d<D)1W^>A3oNB)GCjFfr1}5@3-|1pyZ6xCVHnQ#_co&jwGQ4J^`eZQzkk@nF(E
> z8$EqCvPj3Z(c34Ow9h6_pG}@Vo4kF3N&5_X`V4yd40`(nllIx{>9g6>XS26YFlnEb
> zr%%h%r{(PvOxkD2(`U%jXUN+pn6%HZr_Zpb&#<>oFlnDHo<3VVeYSY}1e5mJ>glu9
> z(`T!<PcUhpZJs{cJbku#`vjBr8S(TP@$?z-_6a8Kv)$8YyQj}~Z=Yb&K07>pc6j>i
> z@b(EN?X%O<XQ!vnPH&%J(mtb}KBJyKquxHjq<wDj^tr{;=N50DVA4Lfdivbz>2s^M
> zPcUhpFvj?M7JFCP=IL{rw@)x>pW8isZuj)L-P<Raw9g$ZGAZ5(cd*Emc(dEVBW-D7
> zWLo%kc_O<!kzL+MFlppYPvlNd<W6rSm^8B66WQ&F?Dj^2Nh5c8B6oQrcX=bhq>;N>
> zr1KuXn?*YB@w<7X^TrJ(Mmm#Zk0<9IPtHBwoM7^tK^UM(GC)Vmc}UHMsR<eqivbD-
> zq~(Sm3@0fJQ0~W`M5cjJPJJdM<*x1k1=DE_1}OJ+1}JgG0m@z70SYEm;|x&lD=f?j
> zRA*vhq;tk_fPx7XF<%&<+*eqlM;3_#l)E}6?Gpwl$FfKmpu`miD45Pv!~qJX(<cm2
> z?#m)!fD%_6pxl+^!~qJX(<cm2?#m)!fD%_6pxl*3;s6EH=@SMh_hpeVK#403Q0~ei
> zae#v9Jf1K>xi5=^0ZLqPfO1zBi31c&r%xE5+?Ped041(CK)EZ6!~qJX(<cm2?#m)!
> zfD%_6pxl*3;s6EH=@SMh_hpeVK#403Q0~eiae#v9^a%r$`?5$Fpu`miD0gL%I6%R4
> z`h)?>eOV+7P~wUMl)JJ>9H3x2eZm0czAO?3C~?IB%3WC`4p1<iK4E}zUls`il(^ym
> z<*qCe2Pl|MpD;kVFN=f$N?dV(a#t3K0~AcBPZ*%wmqo$=C9XI?xhspr0SczmCk#;T
> z%OYWb5?36c+?7S*00q<O69y>vWsxvIi7O6J?#d!@fP(4t2?Lb-vPc-9#1#i9cV&?{
> zK*4nSgaOKZStJZl;)(;5yRt|epkO+E!T{yIED{DNam4}3U0Ea!P%xc7VSsX976}8C
> zxZ(iit}GG<D40&4FhIc~0~9PeK*6K~6ihNeNhAzV5{UzpMB)G?kuX3>Bn(gzi35~G
> z;s7O)FhEHp3{Vn@1C&JK040$yKuIJFP!fp)ltkhHC6O>d!Ezp57@%OmBgRf94p1=R
> zVQ@^0bj~ddP_UeH3j-7^=iK4|1=BgVI6%RKHIS|<j8J1eyvDw)Zr~Tv?;G(?GTND+
> zg75$9&7WDXmy8XodBX}t`}0$FsTsy@Dc0U<g}!Pun%PpqOXDpbvl`$wU;k{$YBNv)
> zs1&QLPBg)sPdY0x;Wobh5`@&{_N`XuSFJ{~A10Im@4*JVn;I{TXj`>BoisMEgkotb
> z8Evno^JU`|YU?#S(uNBf=wX+by{%d<mCd(Hq6SQl$3^y(lHL4>>?x8x#j>ZMKAJrh
> z-8_4$vRc62`C1IDLW$lj-$$gkNqU>5x0Uqv2h!UjeOhVWf)%j;_qk7#^l6qpt)x$X
> zAbnb-%GACW#o(q~xujFLX{f%F-XKC7m0_=xmbl0M7QXO;BX52VkE^rLF}#*aup
> zO45(A^rK4p(GR2_73p(o`lgRapCjpWEPYN%pZh@i9HbB6+mV_+!qYo%9`MlsUhaHx
> z(t9l0$X@dB2Vd6$r@oA>b}tS-FK9S^Y*U=}y6o`c;6sFl<Ht6|X|J<RFAhFgXgGds
> zQ=Im?iF$GHaYMuLW1Hf%*TEJq4nBiuIDTwXoc6rl>czna6Aj0YZHm*Lr`x<Z__U(o
> z_%SaoQV8<p|4cAf%uG8^KNH^aaM8c=I#--781Tva$3KP)Sh|j&-FZ1PneHi;($${m
> zAe%gOJW{LUp}9|MR;0Eb{(7xutkqyWcEeb2{d#TA_|;t4_^<zM*nr^(BMq0=+pX3w
> z;428i4fwJK3+mD8XpujTElInWkHunxM&zr1@$njS*6b<2v*2DVWy(&u7Q9J7xh-~a
> zrYHC4S^fUXot`JRo<3T6vT*CEQ8De}#JG6Xv{=@t`BV6(uo->{?ZNvxEZYARw!)P+
> zhtWtHJ$5lOY1;Y8vT2tJmrYoDkKs+$H2k(*NW=1e2YUMLa%Q3j+|$YF9$2@|Pv(Pl
> z0}obKzxXHLEW0!S74a%XKk*pW!7r>dL^Idz>FhP%y0x}sd|^Yk%P38h@#Xc<+LGl%
> zo#5J!x{vDs>VB>pP!Dk3h<cFgCe%Y*2T>1m-HdvKYYTOf>k#S`*J0E)*Da{iT(_dm
> zaNUMF%XI{F9LmR<+fj@9J5Y=IJ5h`Jqo_swTTqMox1tvHZ$mBW-;P?;zXP?XzYDdf
> ze<x~De>ZAT|1Q*`{@tiW{d-W0`g=epME!eFi~4&}i~9GW7WMB(E$TmjTGW3KwW$9P
> zYEl1T)S~_)s73upQH%PIp%(QYM=k0<fm+mm61AxR6lzg_40NBUKaN_|pFl0@??Wx>
> z??)}_A3!bYA4DzcA3`naA4V<eA3-hZKaE<{e+IRv|14@z|2fp6{`06s{TEP+`Y(d+
> z7xgDmi~3WjMg2BvQGXh>s6T^R)SpEy>K{cd>d&DT_2*HG`o~a<`o~d=`X^9}`U|K<
> z{gbFg{g+US`ir0kMEz5!Mg1kzqW&^!QU5e*QU45TQU7JsqW&wWMg3P%i~6sj7WH38
> zE$XkJ7WL1f7WLmiE$Y9CTGU@fE$Xj<9u)P@p%(SeqZaiqpceHnq89bvLM`gQjat-y
> z2eqhw3ALzy8MUbYE^1N#J=CK9`=~|z4^WHxAEFlZKSC|)uY(>E^*=@}>VJY-)c+K<
> zsQ(#iQU3~RQU7z)qW%}ChnAzcM!1-pY_9B^Jr$tS2d4^Nja3iB1gPWn={5BZoGW#!
> z4X(m!_e_j$)S`t3oHZYp$W&24*pwd~-D;QZ$>0at2-=gGD;>V~bz`A!F8+||SX(sf
> z#$w&9)s49y3gKU_)y!`ftWTh``huF1b*vtQQMtbDTlFXm%Z1;rH?PfE?;+1`>zm!b
> zzF#|aIF0KIUt*DS#>yO&_5INLfab>LHH_2+%U{>d4BQEED+{<AA`{@-ArLrkEZ`Vk
> zfCQEJ=FMp=sApw<^YdJ2wl9^Z!yh=$n?GGNKAgPz@+Rk|Zu!)s=z3Q@2&Z||>MEZP
> z!_bc5hb{vzw!;%UxPeb^_*ha%PPd1wpaJX2xJnUih5a7WA#BE2TE1KPJQIM>I9tH*
> zgu>#08)}*?G*lHInqnrwm<*FcOad+lV2&190e;JOIX)lbgk6s1gRfFfJ(f?B`rrz?
> zN`g<XF3BHINq$Q5OHx04231M$-P<Jv8dOq%k^+)6fXg#VckngZB{ejvqy|cAkfcGl
> zprDfA!>&te4639?N@|p(A-KSxlHkj&OKM_EQ}C2<9yzOtlA0uG7@i<13APKlq@bnN
> z6r`k}B#p37|K4XoGa)szoj0_mW=d+7q$DneDQDawB&$WO$)Y4nl2W*&rjSB}6lzsT
> zAxa8Kk_}&*R8p9b!V#4erlhbWrQrgGN@^jbmUflYLP;%>lz|HxDyfx_T02xyD<!o`
> zQWh?7s3iDa=ROPCqAID4lG<ESJcg?p${B}s50@0#qLLz%6p^GjE?y`kSn_a5?ORn+
> zJ0-PCQUcd46cVg<xTKElDyf5#IwYwNmn;+#EOfY}&K)YLlae|msUKG>6cVg)xTI*8
> zN{UiaRFVd8p+X_S@`g*=(yfxVP|_Aj8pJgUg#;@bE@|s7m9&+Two1|vE>9>VSk!Py
> z+jgs@ZIrZ4l7``ei%Qx~NZZ*~O8Ty{oszao(g<9DQAs-pX~$l*rX7^DLz0rPqd_Hg
> z5mHyLO6sDdE=fwk1savKlaO}qS4lf5X{RLFaKT0;brVwe0hQEEN!^l^h6^|<X%`{w
> zI;fI%QPM6+%D@F3m9(3Xb{|$ryD4e6BxT_Ok4oA@NPCW`q&<|h$0a3VJvym}ka~`)
> zq#jD@k)-%uowS#b_8wPBdnswJBqe%vQZFI(o={1>l+-IpefxCMK0?}eQYG!9q<xaq
> zzh5WqC#3x`m9(Fd_Dj;h0iAS!kPfg<q4X7efRYYK(%?azbdZn^Ce)e^Qqn<58akwt
> z4iVC!ewB2Hk`77I@L`>Fn2-(+sHDS`bXbx`j_9N#gmh$3B^{xpBa)Ons*{cq($Qg+
> zbd-{gN>b{WPC7<N$3|4rF-kfnN%nD_bexcmpH@l7De1T*rBCRj6NGf)tV%jTNhc&J
> zb5bXrB&3t)RMJUGIw?unQ#$DsA)Pv}l1@?5DVNkIzRr2ROTk8dcXGxqs-zet#Uv>n
> z*K3LsQaq`W;*=DZq(nj|B?u{zQb`F)N=Q;)pHAu{q`tID>Z7DSN$T&{N&SS>pHWHu
> zl+-Ut0|Po~fRF~@S^<2NA>XA2C}}{F1_yQ0AR!IrRMH?N4NB6`kWLyRq@lb@8lt2j
> zNg5v3NyCIRJf@O{DQQ@eMn-hf2qBG3sH71}8j+;rX`OVMkWLp=(rHRMElH^}I_V4{
> zotacgXDI26B-v+m(pf?}TU1GBDe0^vrO)Z4bA)tmN+q46q;ry#Ij@t>6VmyTN;*$T
> z=Orn7K_^`xqzlt3=>jEPa7q2Ki#q8dAzhqNNf#;Uq9nzWItebByYF<#%PJ{JNl8gc
> zq;wKoEq6(&t11aMvAF9`DM{+HbrM`CcS-g&m4y3IT#_wG{b`*9*T`K``npQOttBog
> zElC3zodlOvT~cONCE+d+mz0sD!K_Y#E8{LHdqXARh7XsNm879jodg%fUDD`Hm4tgY
> zT+*l{4d-+cTn~3ixtdDCZ5S>oCrKlDos=h}{G3Y4Q&L`%l4Ck)jF86WRnizGjY(2!
> zTqlha()glE8mFXjNwOz&(gYz*+)_yslr$kp>4HvzjRWo(FWgp11xhMNQf5*oO%l@N
> zl1iGSq)AE2UeZaI2<g(YO1eZzmt4|7tf-TUgjBq%l8Tg6l%)8SPMRX5Dfl0A-p>V7
> zlr$wtiIPq#5mM=aN-9xONs{`?ItjKUxQ|`=p-L)KQdyGvr*#tS7;#C{b(J(tNz;-v
> zFr$-Z2x;cAN}8dh8A%$vtdlMi(&Z;A=`tl<mZYI8I_U}_U3sRGu29kyNgBSYldcld
> z)fJU=m6EPX(#SQPbd8X%Jy%KBDCwFcC9mtG>x6Xu6P0wGlCDcqs-lxBgj9K{k}8x`
> zktBOoC(RPl?58SemXc;ADSbmH-5{hJf1;9ZP|^)a%G}gRHwo$HE0uJUl5R>;wyKk=
> zgjD@gl~kpqs!JM-)pSygkZP}0QjL;ok`$lQNpplW_eLenQPP|wCFXU~JR!}ms-$^J
> znwO-$1)a1&NDF_ak`^dwL6Z6xb<!dsE&jPmTBM{!NgBANlWq~xtuIv4ElRp2NrSg_
> z(rrSz{iRB}O-Z*UY3Pnlx<g2JzEVkdDCv$Q4KL}WB|=(ytCE%|X-SesmUYrHAua!f
> zN?N9*Wl2ij)k${=>F!^uq`Q=KSCUfqbkaRSy7yNq=^iEBlO+4TPP$J>_kXF9?o-lz
> zNlHJ^Ne>9=!PhG30VO?<q|8H|^pKDqexs5eQqn_7%0ALbj|l0}uT;__N_ymyhGKP{
> zR41hRw<@VlNp(qzKh{Z)3F+~7D(NvLJ(i@z6P@&gke>WnB|V{}Cz90nR3|+pq^Eza
> zlAco1Q%UN7rjwo#(zCx&NzW+hnIsLY=%f`wTKQX*v_eTMk~H{SCp{;m=f6=&&nfA-
> zBn`dLNiPWL#owu<7nJk@NYS0JX%;pBS2MAMA-4MB23p*=6e(=sJ8Ic4L9p$^V<GFG
> zzicsl{4)D{OmB{wKZkz~n?X2khS|=LKfv8Thh4h`emKG~{)hdn2fH8tAI<ys{Gz{M
> z_zcevegxq+E&hS^Wf*_&x#u1H638F<J@3xHg*9)UP52tvEB+t`-zwo8HE?eY>~pTH
> z+5zYj7HQ$vR@iTjBw?d7-@}Z@$>wF)o;{tkU;_efm}Z-odm4KhP5AYZ%Ia94m@C4!
> z0v!S;X_Jl6I_q8dUD(_X8?TSdLi%!FwWBd$LhYdYs~y3B<+EU;4p;+t54I6GBOiv!
> z>dEXC8<qpGfT>Jj26h%D&|9fE(hzCD?beaZ&RN_*7b$e%qgYuDm18mZOq5KQpqr!R
> z*f2NX5i<?AvR#g+4ftIX5D7>0p@7b#<*anxgB!W?r753Pv%(QOz>-wnoId5pH0X)<
> zn)v^l;QwMxrSQhan{?2CZR}GS)LFb4#hYBPvf4kMN<%UH$8h|xp9p(`?G5-SY`3<I
> znl+<lnDBI4G#24+ua7;d`wN$5+^9CV%1@$#RzolTXiQ}_F;Sd`Rdvn|!1;o$>#&E4
> z_(rUjQS%f3C;nit_cbFY>`MhVrUAS+kNMgEv)>5zMp(>&(zNYX6M{TgJVV!wx?u);
> k4HL_0D`%79y!#9|m3SZ}4*20fB#f^~_-_Ll_+6a;1CLN!@c;k-
>
> literal 0
> HcmV?d00001
>
> diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count
> index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
> GIT binary patch
> literal 244
> zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
> z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
> YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
>
> literal 0
> HcmV?d00001
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
> index 0ce6f8fc72ee..dfb8523c8bf4 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1,4 +1 @@
> /* List of comma-separated changed AML files to ignore */
> -"tests/data/acpi/q35/APIC.type4-count",
> -"tests/data/acpi/q35/DSDT.type4-count",
> -"tests/data/acpi/q35/FACP.type4-count",
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology
2023-08-25 3:36 ` [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology Zhao Liu
@ 2023-09-15 13:11 ` Igor Mammedov
2023-09-19 7:14 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 13:11 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:12 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> Currently, this case just covers the topology with only core and smt
> levels, and doesn't consider more topology layers between socket and
> core.
>
> To cover the fixed case in the commit 196ea60a734c3 ("hw/smbios: Fix
> core count in type4"), add the "die" level in "-smp" as the more
> general topology case.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
PS:
I'd still explain in commit message relations between
-smp and .smbios_core_count2
> ---
> tests/qtest/bios-tables-test.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index a35c753a3a00..8cba1d8126f2 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -1024,10 +1024,12 @@ static void test_acpi_q35_tcg_core_count2(void)
> .required_struct_types = base_required_struct_types,
> .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> .smbios_core_count = 0xFF,
> - .smbios_core_count2 = 275,
> + .smbios_core_count2 = 260,
> };
>
> - test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", &data);
> + test_acpi_one("-machine smbios-entry-point-type=64 "
> + "-smp 260,dies=2,cores=130,threads=1",
> + &data);
> free_test_data(&data);
> }
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count
2023-08-25 3:36 ` [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count Zhao Liu
@ 2023-09-15 13:19 ` Igor Mammedov
2023-09-19 7:13 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 13:19 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:15 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
> type4").
>
> Add this test to cover 2 cases:
> 1. Test thread count field with multiple sockets and multiple dies to
> confirm this field could correctly calculate threads per sockets.
>
> 2. Confirm that field calculation could correctly recognize the
> difference between "-smp maxcpus" and "-smp cpus".
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
PS:
add to commit message an explanation how -smp maps into
smbios_thread_count
> ---
> tests/qtest/bios-tables-test.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 8cba1d8126f2..26474d376633 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -95,6 +95,7 @@ typedef struct {
> uint16_t smbios_cpu_curr_speed;
> uint8_t smbios_core_count;
> uint16_t smbios_core_count2;
> + uint8_t smbios_thread_count;
> uint8_t *required_struct_types;
> int required_struct_types_len;
> int type4_count;
> @@ -640,6 +641,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> SmbiosEntryPointType ep_type)
> {
> uint8_t core_count, expected_core_count = data->smbios_core_count;
> + uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
> uint16_t speed, expected_speed[2];
> uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
> int offset[2];
> @@ -663,6 +665,13 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> g_assert_cmpuint(core_count, ==, expected_core_count);
> }
>
> + thread_count = qtest_readb(data->qts,
> + addr + offsetof(struct smbios_type_4, thread_count));
> +
> + if (expected_thread_count) {
> + g_assert_cmpuint(thread_count, ==, expected_thread_count);
> + }
> +
> if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
> core_count2 = qtest_readw(data->qts,
> addr + offsetof(struct smbios_type_4, core_count2));
> @@ -1033,6 +1042,22 @@ static void test_acpi_q35_tcg_core_count2(void)
> free_test_data(&data);
> }
>
> +static void test_acpi_q35_tcg_thread_count(void)
> +{
> + test_data data = {
> + .machine = MACHINE_Q35,
> + .variant = ".thread-count",
> + .required_struct_types = base_required_struct_types,
> + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> + .smbios_thread_count = 27,
> + };
> +
> + test_acpi_one("-machine smbios-entry-point-type=64 "
> + "-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3",
> + &data);
> + free_test_data(&data);
> +}
> +
> static void test_acpi_q35_tcg_bridge(void)
> {
> test_data data = {};
> @@ -2189,6 +2214,8 @@ int main(int argc, char *argv[])
> test_acpi_q35_tcg_core_count);
> qtest_add_func("acpi/q35/core-count2",
> test_acpi_q35_tcg_core_count2);
> + qtest_add_func("acpi/q35/thread-count",
> + test_acpi_q35_tcg_thread_count);
> }
> qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
> #ifdef CONFIG_POSIX
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2
2023-08-25 3:36 ` [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2 Zhao Liu
@ 2023-09-15 13:29 ` Igor Mammedov
2023-09-19 7:12 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 13:29 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, 25 Aug 2023 11:36:18 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> From: Zhao Liu <zhao1.liu@intel.com>
>
> This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
> type4").
>
> Add this test to cover 2 cases:
> 1. Test thread count2 field with multiple sockets and multiple dies to
> confirm this field could correctly calculate threads per sockets.
>
> 2. Confirm that field calculation could correctly recognize the
> difference between "-smp maxcpus" and "-smp cpus".
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> tests/qtest/bios-tables-test.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 26474d376633..1b0c27e95d26 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -96,6 +96,7 @@ typedef struct {
> uint8_t smbios_core_count;
> uint16_t smbios_core_count2;
> uint8_t smbios_thread_count;
> + uint16_t smbios_thread_count2;
> uint8_t *required_struct_types;
> int required_struct_types_len;
> int type4_count;
> @@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
> uint16_t speed, expected_speed[2];
> uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
> + uint16_t thread_count2, expected_thread_count2 = data->smbios_thread_count2;
> int offset[2];
> int i;
>
> @@ -673,6 +675,8 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> }
>
> if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
> + uint64_t thread_count2_addr;
> +
> core_count2 = qtest_readw(data->qts,
> addr + offsetof(struct smbios_type_4, core_count2));
>
> @@ -680,6 +684,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> if (expected_core_count == 0xFF && expected_core_count2) {
> g_assert_cmpuint(core_count2, ==, expected_core_count2);
> }
> +
> + thread_count2_addr = addr +
> + offsetof(struct smbios_type_4, thread_count2);
> + thread_count2 = qtest_readw(data->qts, thread_count2_addr);
I'd mimic the same code style as used for core_count2 and avoid introducing an extra variable
> +
> + /* Thread Count has reached its limit, checking Thread Count 2 */
> + if (expected_thread_count == 0xFF && expected_thread_count2) {
> + g_assert_cmpuint(thread_count2, ==, expected_thread_count2);
> + }
> }
> }
>
> @@ -1050,6 +1063,7 @@ static void test_acpi_q35_tcg_thread_count(void)
> .required_struct_types = base_required_struct_types,
> .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> .smbios_thread_count = 27,
> + .smbios_thread_count2 = 27,
> };
>
> test_acpi_one("-machine smbios-entry-point-type=64 "
> @@ -1058,6 +1072,23 @@ static void test_acpi_q35_tcg_thread_count(void)
> free_test_data(&data);
> }
>
> +static void test_acpi_q35_tcg_thread_count2(void)
> +{
> + test_data data = {
> + .machine = MACHINE_Q35,
> + .variant = ".thread-count2",
> + .required_struct_types = base_required_struct_types,
> + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> + .smbios_thread_count = 0xFF,
> + .smbios_thread_count2 = 260,
> + };
> +
> + test_acpi_one("-machine smbios-entry-point-type=64 "
> + "-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2",
> + &data);
explain in commit message why abive -smp ==
> + .smbios_thread_count = 0xFF,
> + .smbios_thread_count2 = 260,
> + free_test_data(&data);
> +}
> +
> static void test_acpi_q35_tcg_bridge(void)
> {
> test_data data = {};
> @@ -2216,6 +2247,8 @@ int main(int argc, char *argv[])
> test_acpi_q35_tcg_core_count2);
> qtest_add_func("acpi/q35/thread-count",
> test_acpi_q35_tcg_thread_count);
> + qtest_add_func("acpi/q35/thread-count2",
> + test_acpi_q35_tcg_thread_count2);
> }
> qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
> #ifdef CONFIG_POSIX
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
2023-09-05 6:56 ` Zhao Liu
@ 2023-09-15 13:48 ` Michael S. Tsirkin
2023-09-15 14:30 ` Igor Mammedov
0 siblings, 1 reply; 38+ messages in thread
From: Michael S. Tsirkin @ 2023-09-15 13:48 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael Tokarev, Igor Mammedov, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel, Zhenyu Wang, Zhao Liu
On Tue, Sep 05, 2023 at 02:56:46PM +0800, Zhao Liu wrote:
> Hi Michael,
>
> On Fri, Sep 01, 2023 at 12:55:33PM +0300, Michael Tokarev wrote:
> > Date: Fri, 1 Sep 2023 12:55:33 +0300
> > From: Michael Tokarev <mjt@tls.msk.ru>
> > Subject: Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
> >
> > 25.08.2023 06:36, Zhao Liu wrote:
> > > From: Zhao Liu <zhao1.liu@intel.com>
> > >
> > > Hi all,
> > >
> > > This patchset is the follow up tests of previous topology fixes in
> > > smbios [1].
> > >
> > > In this patchset, add these test cases:
> > >
> > > 1. Add the case to test 2 newly added topology helpers (patch 1):
> > > * machine_topo_get_cores_per_socket()
> > > * machine_topo_get_threads_per_socket()
> > >
> > > 2. Add the cases in bios-tables-test.c to:
> > > * test smbios type4 table count (patch 2-4).
> > > * test smbios type4 core count field (patch 5-7).
> > > * update the test of smbios type4 core count2 field (patch 8-10).
> > > * test smbios type4 thread count (patch 11-13).
> > > * test smbios type4 thread count2 (patch 14-16).
> > >
> > > With the above new cases, cover all commits of [1] in test.
> > >
> > > [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
> >
> > Hmm. I definitely didn't expect such a large patchset.. I asked for just
> > a small, maybe manual (from command-line) reproducer of the original issue,
> > so I can verify it is fixed before applying the change in question to qemu
> > stable trees.
>
> Since these issues are found by coding reading, they are "byproducts" of
> other topology-related work I've been woring on, not directly identified
> by any anomaly...
>
> ...So I'm not quite sure what the consequences of these few misuses of
> topology fields are, and how they might manifest themselves.
>
> > It is a large work. Lemme at least give it a try in the
> > gitlab CI...
>
> The test cases are the ones that clearly define the relevant topology
> issues.
>
>
> Thanks,
> Zhao
I think it's ok, as long as Igor's happy.
> >
> > Philippe, can you pick this up for the misc tree?
> >
> > /mjt
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
2023-09-15 13:48 ` Michael S. Tsirkin
@ 2023-09-15 14:30 ` Igor Mammedov
2023-09-19 6:46 ` Zhao Liu
0 siblings, 1 reply; 38+ messages in thread
From: Igor Mammedov @ 2023-09-15 14:30 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Zhao Liu, Michael Tokarev, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel, Zhenyu Wang, Zhao Liu
On Fri, 15 Sep 2023 09:48:08 -0400
"Michael S. Tsirkin" <mst@redhat.com> wrote:
> On Tue, Sep 05, 2023 at 02:56:46PM +0800, Zhao Liu wrote:
> > Hi Michael,
> >
> > On Fri, Sep 01, 2023 at 12:55:33PM +0300, Michael Tokarev wrote:
> > > Date: Fri, 1 Sep 2023 12:55:33 +0300
> > > From: Michael Tokarev <mjt@tls.msk.ru>
> > > Subject: Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
> > >
> > > 25.08.2023 06:36, Zhao Liu wrote:
> > > > From: Zhao Liu <zhao1.liu@intel.com>
> > > >
> > > > Hi all,
> > > >
> > > > This patchset is the follow up tests of previous topology fixes in
> > > > smbios [1].
> > > >
> > > > In this patchset, add these test cases:
> > > >
> > > > 1. Add the case to test 2 newly added topology helpers (patch 1):
> > > > * machine_topo_get_cores_per_socket()
> > > > * machine_topo_get_threads_per_socket()
> > > >
> > > > 2. Add the cases in bios-tables-test.c to:
> > > > * test smbios type4 table count (patch 2-4).
> > > > * test smbios type4 core count field (patch 5-7).
> > > > * update the test of smbios type4 core count2 field (patch 8-10).
> > > > * test smbios type4 thread count (patch 11-13).
> > > > * test smbios type4 thread count2 (patch 14-16).
> > > >
> > > > With the above new cases, cover all commits of [1] in test.
> > > >
> > > > [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
> > >
> > > Hmm. I definitely didn't expect such a large patchset.. I asked for just
> > > a small, maybe manual (from command-line) reproducer of the original issue,
> > > so I can verify it is fixed before applying the change in question to qemu
> > > stable trees.
> >
> > Since these issues are found by coding reading, they are "byproducts" of
> > other topology-related work I've been woring on, not directly identified
> > by any anomaly...
> >
> > ...So I'm not quite sure what the consequences of these few misuses of
> > topology fields are, and how they might manifest themselves.
> >
> > > It is a large work. Lemme at least give it a try in the
> > > gitlab CI...
> >
> > The test cases are the ones that clearly define the relevant topology
> > issues.
> >
> >
> > Thanks,
> > Zhao
>
> I think it's ok, as long as Igor's happy.
series looks fine to me
(modulo cosmetic issues and better commit messages as noted in per patch review)
>
> > >
> > > Philippe, can you pick this up for the misc tree?
> > >
> > > /mjt
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
2023-09-15 14:30 ` Igor Mammedov
@ 2023-09-19 6:46 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 6:46 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S. Tsirkin, Michael Tokarev, Ani Sinha, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
qemu-devel, Zhenyu Wang, Zhao Liu
On Fri, Sep 15, 2023 at 04:30:55PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 16:30:55 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 15 Sep 2023 09:48:08 -0400
> "Michael S. Tsirkin" <mst@redhat.com> wrote:
>
> > On Tue, Sep 05, 2023 at 02:56:46PM +0800, Zhao Liu wrote:
> > > Hi Michael,
> > >
> > > On Fri, Sep 01, 2023 at 12:55:33PM +0300, Michael Tokarev wrote:
> > > > Date: Fri, 1 Sep 2023 12:55:33 +0300
> > > > From: Michael Tokarev <mjt@tls.msk.ru>
> > > > Subject: Re: [PATCH 00/16] tests: Add CPU topology related smbios test cases
> > > >
> > > > 25.08.2023 06:36, Zhao Liu wrote:
> > > > > From: Zhao Liu <zhao1.liu@intel.com>
> > > > >
> > > > > Hi all,
> > > > >
> > > > > This patchset is the follow up tests of previous topology fixes in
> > > > > smbios [1].
> > > > >
> > > > > In this patchset, add these test cases:
> > > > >
> > > > > 1. Add the case to test 2 newly added topology helpers (patch 1):
> > > > > * machine_topo_get_cores_per_socket()
> > > > > * machine_topo_get_threads_per_socket()
> > > > >
> > > > > 2. Add the cases in bios-tables-test.c to:
> > > > > * test smbios type4 table count (patch 2-4).
> > > > > * test smbios type4 core count field (patch 5-7).
> > > > > * update the test of smbios type4 core count2 field (patch 8-10).
> > > > > * test smbios type4 thread count (patch 11-13).
> > > > > * test smbios type4 thread count2 (patch 14-16).
> > > > >
> > > > > With the above new cases, cover all commits of [1] in test.
> > > > >
> > > > > [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg06225.html
> > > >
> > > > Hmm. I definitely didn't expect such a large patchset.. I asked for just
> > > > a small, maybe manual (from command-line) reproducer of the original issue,
> > > > so I can verify it is fixed before applying the change in question to qemu
> > > > stable trees.
> > >
> > > Since these issues are found by coding reading, they are "byproducts" of
> > > other topology-related work I've been woring on, not directly identified
> > > by any anomaly...
> > >
> > > ...So I'm not quite sure what the consequences of these few misuses of
> > > topology fields are, and how they might manifest themselves.
> > >
> > > > It is a large work. Lemme at least give it a try in the
> > > > gitlab CI...
> > >
> > > The test cases are the ones that clearly define the relevant topology
> > > issues.
> > >
> > >
> > > Thanks,
> > > Zhao
> >
> > I think it's ok, as long as Igor's happy.
>
> series looks fine to me
> (modulo cosmetic issues and better commit messages as noted in per patch review)
Thanks Igor!
-Zhao
>
> >
> > > >
> > > > Philippe, can you pick this up for the misc tree?
> > > >
> > > > /mjt
> >
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2
2023-09-15 13:29 ` Igor Mammedov
@ 2023-09-19 7:12 ` Zhao Liu
2023-09-19 8:01 ` Igor Mammedov
0 siblings, 1 reply; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:12 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
Hi Igor,
On Fri, Sep 15, 2023 at 03:29:07PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 15:29:07 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 15/16] tests: bios-tables-test: Add test for smbios
> type4 thread count2
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:18 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
> > type4").
> >
> > Add this test to cover 2 cases:
> > 1. Test thread count2 field with multiple sockets and multiple dies to
> > confirm this field could correctly calculate threads per sockets.
> >
> > 2. Confirm that field calculation could correctly recognize the
> > difference between "-smp maxcpus" and "-smp cpus".
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > ---
> > tests/qtest/bios-tables-test.c | 33 +++++++++++++++++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> > index 26474d376633..1b0c27e95d26 100644
> > --- a/tests/qtest/bios-tables-test.c
> > +++ b/tests/qtest/bios-tables-test.c
> > @@ -96,6 +96,7 @@ typedef struct {
> > uint8_t smbios_core_count;
> > uint16_t smbios_core_count2;
> > uint8_t smbios_thread_count;
> > + uint16_t smbios_thread_count2;
> > uint8_t *required_struct_types;
> > int required_struct_types_len;
> > int type4_count;
> > @@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
> > uint16_t speed, expected_speed[2];
> > uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
> > + uint16_t thread_count2, expected_thread_count2 = data->smbios_thread_count2;
> > int offset[2];
> > int i;
> >
> > @@ -673,6 +675,8 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > }
> >
> > if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
> > + uint64_t thread_count2_addr;
> > +
> > core_count2 = qtest_readw(data->qts,
> > addr + offsetof(struct smbios_type_4, core_count2));
> >
> > @@ -680,6 +684,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > if (expected_core_count == 0xFF && expected_core_count2) {
> > g_assert_cmpuint(core_count2, ==, expected_core_count2);
> > }
> > +
> > + thread_count2_addr = addr +
> > + offsetof(struct smbios_type_4, thread_count2);
> > + thread_count2 = qtest_readw(data->qts, thread_count2_addr);
>
> I'd mimic the same code style as used for core_count2 and avoid introducing an extra variable
I'm not sure about the style of this case, since the code line is still
too long, so which style should I pick? ;-)
thread_count2 = qtest_readw(data->qts,
addr + offsetof(struct smbios_type_4,
thread_count2));
or,
thread_count2 = qtest_readw(data->qts,
addr + offsetof(struct smbios_type_4,
thread_count2));
>
> > +
> > + /* Thread Count has reached its limit, checking Thread Count 2 */
> > + if (expected_thread_count == 0xFF && expected_thread_count2) {
> > + g_assert_cmpuint(thread_count2, ==, expected_thread_count2);
> > + }
> > }
> > }
> >
> > @@ -1050,6 +1063,7 @@ static void test_acpi_q35_tcg_thread_count(void)
> > .required_struct_types = base_required_struct_types,
> > .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > .smbios_thread_count = 27,
> > + .smbios_thread_count2 = 27,
> > };
> >
> > test_acpi_one("-machine smbios-entry-point-type=64 "
> > @@ -1058,6 +1072,23 @@ static void test_acpi_q35_tcg_thread_count(void)
> > free_test_data(&data);
> > }
> >
> > +static void test_acpi_q35_tcg_thread_count2(void)
> > +{
> > + test_data data = {
> > + .machine = MACHINE_Q35,
> > + .variant = ".thread-count2",
> > + .required_struct_types = base_required_struct_types,
> > + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > + .smbios_thread_count = 0xFF,
> > + .smbios_thread_count2 = 260,
> > + };
> > +
> > + test_acpi_one("-machine smbios-entry-point-type=64 "
> > + "-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2",
> > + &data);
>
> explain in commit message why abive -smp ==
Ok, this is used to test if we could correctly distinguish smp.cpus and smp.maxcpus.
Thanks,
Zhao
> > + .smbios_thread_count = 0xFF,
> > + .smbios_thread_count2 = 260,
>
>
> > + free_test_data(&data);
> > +}
> > +
> > static void test_acpi_q35_tcg_bridge(void)
> > {
> > test_data data = {};
> > @@ -2216,6 +2247,8 @@ int main(int argc, char *argv[])
> > test_acpi_q35_tcg_core_count2);
> > qtest_add_func("acpi/q35/thread-count",
> > test_acpi_q35_tcg_thread_count);
> > + qtest_add_func("acpi/q35/thread-count2",
> > + test_acpi_q35_tcg_thread_count2);
> > }
> > qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
> > #ifdef CONFIG_POSIX
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count
2023-09-15 13:19 ` Igor Mammedov
@ 2023-09-19 7:13 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:13 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, Sep 15, 2023 at 03:19:02PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 15:19:02 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 12/16] tests: bios-tables-test: Add test for smbios
> type4 thread count
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:15 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
> > type4").
> >
> > Add this test to cover 2 cases:
> > 1. Test thread count field with multiple sockets and multiple dies to
> > confirm this field could correctly calculate threads per sockets.
> >
> > 2. Confirm that field calculation could correctly recognize the
> > difference between "-smp maxcpus" and "-smp cpus".
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
Thanks!
>
> PS:
> add to commit message an explanation how -smp maps into
> smbios_thread_count
Ok.
-Zhao
>
> > ---
> > tests/qtest/bios-tables-test.c | 27 +++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> > index 8cba1d8126f2..26474d376633 100644
> > --- a/tests/qtest/bios-tables-test.c
> > +++ b/tests/qtest/bios-tables-test.c
> > @@ -95,6 +95,7 @@ typedef struct {
> > uint16_t smbios_cpu_curr_speed;
> > uint8_t smbios_core_count;
> > uint16_t smbios_core_count2;
> > + uint8_t smbios_thread_count;
> > uint8_t *required_struct_types;
> > int required_struct_types_len;
> > int type4_count;
> > @@ -640,6 +641,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > SmbiosEntryPointType ep_type)
> > {
> > uint8_t core_count, expected_core_count = data->smbios_core_count;
> > + uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
> > uint16_t speed, expected_speed[2];
> > uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
> > int offset[2];
> > @@ -663,6 +665,13 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > g_assert_cmpuint(core_count, ==, expected_core_count);
> > }
> >
> > + thread_count = qtest_readb(data->qts,
> > + addr + offsetof(struct smbios_type_4, thread_count));
> > +
> > + if (expected_thread_count) {
> > + g_assert_cmpuint(thread_count, ==, expected_thread_count);
> > + }
> > +
> > if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
> > core_count2 = qtest_readw(data->qts,
> > addr + offsetof(struct smbios_type_4, core_count2));
> > @@ -1033,6 +1042,22 @@ static void test_acpi_q35_tcg_core_count2(void)
> > free_test_data(&data);
> > }
> >
> > +static void test_acpi_q35_tcg_thread_count(void)
> > +{
> > + test_data data = {
> > + .machine = MACHINE_Q35,
> > + .variant = ".thread-count",
> > + .required_struct_types = base_required_struct_types,
> > + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > + .smbios_thread_count = 27,
> > + };
> > +
> > + test_acpi_one("-machine smbios-entry-point-type=64 "
> > + "-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3",
> > + &data);
> > + free_test_data(&data);
> > +}
> > +
> > static void test_acpi_q35_tcg_bridge(void)
> > {
> > test_data data = {};
> > @@ -2189,6 +2214,8 @@ int main(int argc, char *argv[])
> > test_acpi_q35_tcg_core_count);
> > qtest_add_func("acpi/q35/core-count2",
> > test_acpi_q35_tcg_core_count2);
> > + qtest_add_func("acpi/q35/thread-count",
> > + test_acpi_q35_tcg_thread_count);
> > }
> > qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
> > #ifdef CONFIG_POSIX
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology
2023-09-15 13:11 ` Igor Mammedov
@ 2023-09-19 7:14 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:14 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, Sep 15, 2023 at 03:11:57PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 15:11:57 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 09/16] tests: bios-tables-test: Extend core count2 test
> to cover general topology
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:12 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > Currently, this case just covers the topology with only core and smt
> > levels, and doesn't consider more topology layers between socket and
> > core.
> >
> > To cover the fixed case in the commit 196ea60a734c3 ("hw/smbios: Fix
> > core count in type4"), add the "die" level in "-smp" as the more
> > general topology case.
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
Thanks!
>
> PS:
> I'd still explain in commit message relations between
> -smp and .smbios_core_count2
Ok.
-Zhao
>
> > ---
> > tests/qtest/bios-tables-test.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> > index a35c753a3a00..8cba1d8126f2 100644
> > --- a/tests/qtest/bios-tables-test.c
> > +++ b/tests/qtest/bios-tables-test.c
> > @@ -1024,10 +1024,12 @@ static void test_acpi_q35_tcg_core_count2(void)
> > .required_struct_types = base_required_struct_types,
> > .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > .smbios_core_count = 0xFF,
> > - .smbios_core_count2 = 275,
> > + .smbios_core_count2 = 260,
> > };
> >
> > - test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", &data);
> > + test_acpi_one("-machine smbios-entry-point-type=64 "
> > + "-smp 260,dies=2,cores=130,threads=1",
> > + &data);
> > free_test_data(&data);
> > }
> >
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers
2023-09-15 12:31 ` Igor Mammedov
@ 2023-09-19 7:18 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:18 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, Sep 15, 2023 at 02:31:38PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 14:31:38 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 01/16] tests: test-smp-parse: Add the test for
> cores/threads per socket helpers
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:04 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > Use the different ways to calculate cores/threads per socket, so that
> > the new CPU topology levels won't be missed in these 2 helpes:
> >
> > * machine_topo_get_cores_per_socket()
> > * machine_topo_get_threads_per_socket()
> >
> > Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
> > threads per socket").
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
Thanks!
-Zhao
>
> > ---
> > tests/unit/test-smp-parse.c | 67 ++++++++++++++++++++++++++++++-------
> > 1 file changed, 54 insertions(+), 13 deletions(-)
> >
> > diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
> > index fdc39a846ca6..24972666a74d 100644
> > --- a/tests/unit/test-smp-parse.c
> > +++ b/tests/unit/test-smp-parse.c
> > @@ -394,20 +394,47 @@ static char *smp_config_to_string(const SMPConfiguration *config)
> > config->has_maxcpus ? "true" : "false", config->maxcpus);
> > }
> >
> > -static char *cpu_topology_to_string(const CpuTopology *topo)
> > +/* Use the different calculation than machine_topo_get_threads_per_socket(). */
> > +static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo)
> > +{
> > + /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
> > + if (!topo->sockets) {
> > + return 0;
> > + } else {
> > + return topo->max_cpus / topo->sockets;
> > + }
> > +}
> > +
> > +/* Use the different calculation than machine_topo_get_cores_per_socket(). */
> > +static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo)
> > +{
> > + /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
> > + if (!topo->threads) {
> > + return 0;
> > + } else {
> > + return cpu_topology_get_threads_per_socket(topo) / topo->threads;
> > + }
> > +}
> > +
> > +static char *cpu_topology_to_string(const CpuTopology *topo,
> > + unsigned int threads_per_socket,
> > + unsigned int cores_per_socket)
> > {
> > return g_strdup_printf(
> > "(CpuTopology) {\n"
> > - " .cpus = %u,\n"
> > - " .sockets = %u,\n"
> > - " .dies = %u,\n"
> > - " .clusters = %u,\n"
> > - " .cores = %u,\n"
> > - " .threads = %u,\n"
> > - " .max_cpus = %u,\n"
> > + " .cpus = %u,\n"
> > + " .sockets = %u,\n"
> > + " .dies = %u,\n"
> > + " .clusters = %u,\n"
> > + " .cores = %u,\n"
> > + " .threads = %u,\n"
> > + " .max_cpus = %u,\n"
> > + " .threads_per_socket = %u,\n"
> > + " .cores_per_socket = %u,\n"
> > "}",
> > topo->cpus, topo->sockets, topo->dies, topo->clusters,
> > - topo->cores, topo->threads, topo->max_cpus);
> > + topo->cores, topo->threads, topo->max_cpus,
> > + threads_per_socket, cores_per_socket);
> > }
> >
> > static void check_parse(MachineState *ms, const SMPConfiguration *config,
> > @@ -415,14 +442,26 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
> > bool is_valid)
> > {
> > g_autofree char *config_str = smp_config_to_string(config);
> > - g_autofree char *expect_topo_str = cpu_topology_to_string(expect_topo);
> > - g_autofree char *output_topo_str = NULL;
> > + g_autofree char *expect_topo_str = NULL, *output_topo_str = NULL;
> > + unsigned int expect_threads_per_socket, expect_cores_per_socket;
> > + unsigned int ms_threads_per_socket, ms_cores_per_socket;
> > Error *err = NULL;
> >
> > + expect_threads_per_socket =
> > + cpu_topology_get_threads_per_socket(expect_topo);
> > + expect_cores_per_socket =
> > + cpu_topology_get_cores_per_socket(expect_topo);
> > + expect_topo_str = cpu_topology_to_string(expect_topo,
> > + expect_threads_per_socket,
> > + expect_cores_per_socket);
> > +
> > /* call the generic parser */
> > machine_parse_smp_config(ms, config, &err);
> >
> > - output_topo_str = cpu_topology_to_string(&ms->smp);
> > + ms_threads_per_socket = machine_topo_get_threads_per_socket(ms);
> > + ms_cores_per_socket = machine_topo_get_cores_per_socket(ms);
> > + output_topo_str = cpu_topology_to_string(&ms->smp, ms_threads_per_socket,
> > + ms_cores_per_socket);
> >
> > /* when the configuration is supposed to be valid */
> > if (is_valid) {
> > @@ -433,7 +472,9 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
> > (ms->smp.clusters == expect_topo->clusters) &&
> > (ms->smp.cores == expect_topo->cores) &&
> > (ms->smp.threads == expect_topo->threads) &&
> > - (ms->smp.max_cpus == expect_topo->max_cpus)) {
> > + (ms->smp.max_cpus == expect_topo->max_cpus) &&
> > + (ms_threads_per_socket == expect_threads_per_socket) &&
> > + (ms_cores_per_socket == expect_cores_per_socket)) {
> > return;
> > }
> >
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count
2023-09-15 12:54 ` Igor Mammedov
@ 2023-09-19 7:20 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:20 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, Sep 15, 2023 at 02:54:32PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 14:54:32 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 03/16] tests: bios-tables-test: Add test for smbios
> type4 count
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:06 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
> > calculation").
> >
> > Test the count of type4 tables for multiple sockets case.
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > ---
> > tests/qtest/bios-tables-test.c | 33 ++++++++++++++++++++++++++++++++-
> > 1 file changed, 32 insertions(+), 1 deletion(-)
> >
> > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> > index 47ba20b9579b..8679255449cf 100644
> > --- a/tests/qtest/bios-tables-test.c
> > +++ b/tests/qtest/bios-tables-test.c
> > @@ -97,6 +97,7 @@ typedef struct {
> > uint16_t smbios_core_count2;
> > uint8_t *required_struct_types;
> > int required_struct_types_len;
> > + int type4_count;
> > QTestState *qts;
> > } test_data;
> >
> > @@ -673,12 +674,21 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > }
> > }
> >
> > +static void smbios_type4_count_test(test_data *data, int type4_count)
> > +{
> > + int expected_type4_count = data->type4_count;
> > +
> > + if (expected_type4_count) {
> > + g_assert_cmpuint(type4_count, ==, expected_type4_count);
> > + }
> > +}
> > +
> > static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
> > {
> > DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
> >
> > SmbiosEntryPoint *ep_table = &data->smbios_ep_table;
> > - int i = 0, len, max_len = 0;
> > + int i = 0, len, max_len = 0, type4_count = 0;
> > uint8_t type, prv, crt;
> > uint64_t addr;
> >
> > @@ -704,6 +714,7 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
> >
> > if (type == 4) {
> > smbios_cpu_test(data, addr, ep_type);
> > + type4_count++;
> > }
> >
> > /* seek to end of unformatted string area of this struct ("\0\0") */
> > @@ -747,6 +758,8 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
> > for (i = 0; i < data->required_struct_types_len; i++) {
> > g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
> > }
> > +
> > + smbios_type4_count_test(data, type4_count);
> > }
> >
> > static void test_acpi_load_tables(test_data *data)
> > @@ -970,6 +983,22 @@ static void test_acpi_q35_tcg(void)
> > free_test_data(&data);
> > }
> >
> > +static void test_acpi_q35_tcg_type4_count(void)
> > +{
> > + test_data data = {
> > + .machine = MACHINE_Q35,
> > + .variant = ".type4-count",
> > + .required_struct_types = base_required_struct_types,
> > + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > + .type4_count = 5,
> > + };
> > +
> > + test_acpi_one("-machine smbios-entry-point-type=64 "
> > + "-smp cpus=100,maxcpus=120,sockets=5,"
> > + "dies=2,cores=4,threads=3", &data);
>
> I'd add to commit message an explanation why above topology was picked up
Ok. I'll. Because it defines mutiple sockets and smbios build type4 per
socket.
Thanks,
Zhao
>
> > + free_test_data(&data);
> > +}
> > +
> > static void test_acpi_q35_tcg_core_count2(void)
> > {
> > test_data data = {
> > @@ -2135,6 +2164,8 @@ int main(int argc, char *argv[])
> > if (has_kvm) {
> > qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
> > qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
> > + qtest_add_func("acpi/q35/type4-count",
> > + test_acpi_q35_tcg_type4_count);
> > qtest_add_func("acpi/q35/core-count2",
> > test_acpi_q35_tcg_core_count2);
> > }
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count
2023-09-15 13:03 ` Igor Mammedov
@ 2023-09-19 7:21 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:21 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Fri, Sep 15, 2023 at 03:03:07PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 15:03:07 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 06/16] tests: bios-tables-test: Add test for smbios
> type4 core count
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:09 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
> > type4").
> >
> > Test the core count field of type4 table for multiple sockets/dies case.
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > ---
> > tests/qtest/bios-tables-test.c | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> > index 8679255449cf..a35c753a3a00 100644
> > --- a/tests/qtest/bios-tables-test.c
> > +++ b/tests/qtest/bios-tables-test.c
> > @@ -999,6 +999,23 @@ static void test_acpi_q35_tcg_type4_count(void)
> > free_test_data(&data);
> > }
> >
> > +static void test_acpi_q35_tcg_core_count(void)
> > +{
> > + test_data data = {
> > + .machine = MACHINE_Q35,
> > + .variant = ".core-count",
> > + .required_struct_types = base_required_struct_types,
> > + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > + .smbios_core_count = 9,
> > + .smbios_core_count2 = 9,
> > + };
> > +
> > + test_acpi_one("-machine smbios-entry-point-type=64 "
> > + "-smp 54,sockets=2,dies=3,cores=3,threads=3",
>
> ditto as for 3/16
> It's not obvious why this topology is used and how it correlates to smbios_core_*
> so describe setup in commit message
Ok. I'll.
Thanks,
Zhao
>
> > + &data);
> > + free_test_data(&data);
> > +}
> > +
> > static void test_acpi_q35_tcg_core_count2(void)
> > {
> > test_data data = {
> > @@ -2166,6 +2183,8 @@ int main(int argc, char *argv[])
> > qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
> > qtest_add_func("acpi/q35/type4-count",
> > test_acpi_q35_tcg_type4_count);
> > + qtest_add_func("acpi/q35/core-count",
> > + test_acpi_q35_tcg_core_count);
> > qtest_add_func("acpi/q35/core-count2",
> > test_acpi_q35_tcg_core_count2);
> > }
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test
2023-09-15 13:05 ` Igor Mammedov
@ 2023-09-19 7:26 ` Zhao Liu
0 siblings, 0 replies; 38+ messages in thread
From: Zhao Liu @ 2023-09-19 7:26 UTC (permalink / raw)
To: Igor Mammedov
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
Hi Igor,
On Fri, Sep 15, 2023 at 03:05:10PM +0200, Igor Mammedov wrote:
> Date: Fri, 15 Sep 2023 15:05:10 +0200
> From: Igor Mammedov <imammedo@redhat.com>
> Subject: Re: [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries
> for type4 count test
> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
>
> On Fri, 25 Aug 2023 11:36:07 +0800
> Zhao Liu <zhao1.liu@linux.intel.com> wrote:
>
> copy/past mistake in subj?
>
> shouldn't it be for 'smbios type4 count'?
Thanks! I just thought the subject is too long and omitted the word
"smbios", I'll correct it as:
"tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test"
-Zhao
>
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > Following the guidelines in tests/qtest/bios-tables-test.c, this
> > is step 5 and 6.
> >
> > Changes in the tables:
> > FACP:
> >
> > +/*
> > + * Intel ACPI Component Architecture
> > + * AML/ASL+ Disassembler version 20200925 (64-bit version)
> > + * Copyright (c) 2000 - 2020 Intel Corporation
> > + *
> > + * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
> > + *
> > + * ACPI Data Table [FACP]
> > + *
> > + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
> > + */
> > +
> > +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
> > +[004h 0004 4] Table Length : 000000F4
> > +[008h 0008 1] Revision : 03
> > +[009h 0009 1] Checksum : B3
> > +[00Ah 0010 6] Oem ID : "BOCHS "
> > +[010h 0016 8] Oem Table ID : "BXPC "
> > +[018h 0024 4] Oem Revision : 00000001
> > +[01Ch 0028 4] Asl Compiler ID : "BXPC"
> > +[020h 0032 4] Asl Compiler Revision : 00000001
> > +
> > +[024h 0036 4] FACS Address : 00000000
> > +[028h 0040 4] DSDT Address : 00000000
> > +[02Ch 0044 1] Model : 01
> > +[02Dh 0045 1] PM Profile : 00 [Unspecified]
> > +[02Eh 0046 2] SCI Interrupt : 0009
> > +[030h 0048 4] SMI Command Port : 000000B2
> > +[034h 0052 1] ACPI Enable Value : 02
> > +[035h 0053 1] ACPI Disable Value : 03
> > +[036h 0054 1] S4BIOS Command : 00
> > +[037h 0055 1] P-State Control : 00
> > +[038h 0056 4] PM1A Event Block Address : 00000600
> > +[03Ch 0060 4] PM1B Event Block Address : 00000000
> > +[040h 0064 4] PM1A Control Block Address : 00000604
> > +[044h 0068 4] PM1B Control Block Address : 00000000
> > +[048h 0072 4] PM2 Control Block Address : 00000000
> > +[04Ch 0076 4] PM Timer Block Address : 00000608
> > +[050h 0080 4] GPE0 Block Address : 00000620
> > +[054h 0084 4] GPE1 Block Address : 00000000
> > +[058h 0088 1] PM1 Event Block Length : 04
> > +[059h 0089 1] PM1 Control Block Length : 02
> > +[05Ah 0090 1] PM2 Control Block Length : 00
> > +[05Bh 0091 1] PM Timer Block Length : 04
> > +[05Ch 0092 1] GPE0 Block Length : 10
> > +[05Dh 0093 1] GPE1 Block Length : 00
> > +[05Eh 0094 1] GPE1 Base Offset : 00
> > +[05Fh 0095 1] _CST Support : 00
> > +[060h 0096 2] C2 Latency : 0FFF
> > +[062h 0098 2] C3 Latency : 0FFF
> > +[064h 0100 2] CPU Cache Size : 0000
> > +[066h 0102 2] Cache Flush Stride : 0000
> > +[068h 0104 1] Duty Cycle Offset : 00
> > +[069h 0105 1] Duty Cycle Width : 00
> > +[06Ah 0106 1] RTC Day Alarm Index : 00
> > +[06Bh 0107 1] RTC Month Alarm Index : 00
> > +[06Ch 0108 1] RTC Century Index : 32
> > +[06Dh 0109 2] Boot Flags (decoded below) : 0002
> > + Legacy Devices Supported (V2) : 0
> > + 8042 Present on ports 60/64 (V2) : 1
> > + VGA Not Present (V4) : 0
> > + MSI Not Supported (V4) : 0
> > + PCIe ASPM Not Supported (V4) : 0
> > + CMOS RTC Not Present (V5) : 0
> > +[06Fh 0111 1] Reserved : 00
> > +[070h 0112 4] Flags (decoded below) : 000484A5
> > + WBINVD instruction is operational (V1) : 1
> > + WBINVD flushes all caches (V1) : 0
> > + All CPUs support C1 (V1) : 1
> > + C2 works on MP system (V1) : 0
> > + Control Method Power Button (V1) : 0
> > + Control Method Sleep Button (V1) : 1
> > + RTC wake not in fixed reg space (V1) : 0
> > + RTC can wake system from S4 (V1) : 1
> > + 32-bit PM Timer (V1) : 0
> > + Docking Supported (V1) : 0
> > + Reset Register Supported (V2) : 1
> > + Sealed Case (V3) : 0
> > + Headless - No Video (V3) : 0
> > + Use native instr after SLP_TYPx (V3) : 0
> > + PCIEXP_WAK Bits Supported (V4) : 0
> > + Use Platform Timer (V4) : 1
> > + RTC_STS valid on S4 wake (V4) : 0
> > + Remote Power-on capable (V4) : 0
> > + Use APIC Cluster Model (V4) : 1
> > + Use APIC Physical Destination Mode (V4) : 0
> > + Hardware Reduced (V5) : 0
> > + Low Power S0 Idle (V5) : 0
> > +
> > +[074h 0116 12] Reset Register : [Generic Address Structure]
> > +[074h 0116 1] Space ID : 01 [SystemIO]
> > +[075h 0117 1] Bit Width : 08
> > +[076h 0118 1] Bit Offset : 00
> > +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[078h 0120 8] Address : 0000000000000CF9
> > +
> > +[080h 0128 1] Value to cause reset : 0F
> > +[081h 0129 2] ARM Flags (decoded below) : 0000
> > + PSCI Compliant : 0
> > + Must use HVC for PSCI : 0
> > +
> > +[083h 0131 1] FADT Minor Revision : 00
> > +[084h 0132 8] FACS Address : 0000000000000000
> > +[08Ch 0140 8] DSDT Address : 0000000000000000
> > +[094h 0148 12] PM1A Event Block : [Generic Address Structure]
> > +[094h 0148 1] Space ID : 01 [SystemIO]
> > +[095h 0149 1] Bit Width : 20
> > +[096h 0150 1] Bit Offset : 00
> > +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[098h 0152 8] Address : 0000000000000600
> > +
> > +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
> > +[0A0h 0160 1] Space ID : 00 [SystemMemory]
> > +[0A1h 0161 1] Bit Width : 00
> > +[0A2h 0162 1] Bit Offset : 00
> > +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0A4h 0164 8] Address : 0000000000000000
> > +
> > +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
> > +[0ACh 0172 1] Space ID : 01 [SystemIO]
> > +[0ADh 0173 1] Bit Width : 10
> > +[0AEh 0174 1] Bit Offset : 00
> > +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0B0h 0176 8] Address : 0000000000000604
> > +
> > +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
> > +[0B8h 0184 1] Space ID : 00 [SystemMemory]
> > +[0B9h 0185 1] Bit Width : 00
> > +[0BAh 0186 1] Bit Offset : 00
> > +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0BCh 0188 8] Address : 0000000000000000
> > +
> > +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
> > +[0C4h 0196 1] Space ID : 00 [SystemMemory]
> > +[0C5h 0197 1] Bit Width : 00
> > +[0C6h 0198 1] Bit Offset : 00
> > +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0C8h 0200 8] Address : 0000000000000000
> > +
> > +[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
> > +[0D0h 0208 1] Space ID : 01 [SystemIO]
> > +[0D1h 0209 1] Bit Width : 20
> > +[0D2h 0210 1] Bit Offset : 00
> > +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0D4h 0212 8] Address : 0000000000000608
> > +
> > +[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
> > +[0DCh 0220 1] Space ID : 01 [SystemIO]
> > +[0DDh 0221 1] Bit Width : 80
> > +[0DEh 0222 1] Bit Offset : 00
> > +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0E0h 0224 8] Address : 0000000000000620
> > +
> > +[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
> > +[0E8h 0232 1] Space ID : 00 [SystemMemory]
> > +[0E9h 0233 1] Bit Width : 00
> > +[0EAh 0234 1] Bit Offset : 00
> > +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
> > +[0ECh 0236 8] Address : 0000000000000000
> > +
> > ...
> >
> > APIC:
> >
> > +/*
> > + * Intel ACPI Component Architecture
> > + * AML/ASL+ Disassembler version 20200925 (64-bit version)
> > + * Copyright (c) 2000 - 2020 Intel Corporation
> > + *
> > + * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
> > + *
> > + * ACPI Data Table [APIC]
> > + *
> > + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
> > + */
> > +
> > +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
> > +[004h 0004 4] Table Length : 00000430
> > +[008h 0008 1] Revision : 03
> > +[009h 0009 1] Checksum : C5
> > +[00Ah 0010 6] Oem ID : "BOCHS "
> > +[010h 0016 8] Oem Table ID : "BXPC "
> > +[018h 0024 4] Oem Revision : 00000001
> > +[01Ch 0028 4] Asl Compiler ID : "BXPC"
> > +[020h 0032 4] Asl Compiler Revision : 00000001
> > +
> > +[024h 0036 4] Local Apic Address : FEE00000
> > +[028h 0040 4] Flags (decoded below) : 00000001
> > + PC-AT Compatibility : 1
> > +
> > +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
> > +[02Dh 0045 1] Length : 08
> > +[02Eh 0046 1] Processor ID : 00
> > +[02Fh 0047 1] Local Apic ID : 00
> > +[030h 0048 4] Flags (decoded below) : 00000001
> > + Processor Enabled : 1
> > + Runtime Online Capable : 0
> > +
> > +[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
> > +[035h 0053 1] Length : 08
> > +[036h 0054 1] Processor ID : 01
> > +[037h 0055 1] Local Apic ID : 01
> > +[038h 0056 4] Flags (decoded below) : 00000001
> > + Processor Enabled : 1
> > + Runtime Online Capable : 0
> >
> > [snip]
> >
> > +[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
> > +[3E5h 0997 1] Length : 08
> > +[3E6h 0998 1] Processor ID : 77
> > +[3E7h 0999 1] Local Apic ID : 9E
> > +[3E8h 1000 4] Flags (decoded below) : 00000000
> > + Processor Enabled : 0
> > + Runtime Online Capable : 0
> > +
> > +[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
> > +[3EDh 1005 1] Length : 0C
> > +[3EEh 1006 1] I/O Apic ID : 00
> > +[3EFh 1007 1] Reserved : 00
> > +[3F0h 1008 4] Address : FEC00000
> > +[3F4h 1012 4] Interrupt : 00000000
> > +
> > +[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
> > +[3F9h 1017 1] Length : 0A
> > +[3FAh 1018 1] Bus : 00
> > +[3FBh 1019 1] Source : 00
> > +[3FCh 1020 4] Interrupt : 00000002
> > +[400h 1024 2] Flags (decoded below) : 0000
> > + Polarity : 0
> > + Trigger Mode : 0
> > +
> > +[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
> > +[403h 1027 1] Length : 0A
> > +[404h 1028 1] Bus : 00
> > +[405h 1029 1] Source : 05
> > +[406h 1030 4] Interrupt : 00000005
> > +[40Ah 1034 2] Flags (decoded below) : 000D
> > + Polarity : 1
> > + Trigger Mode : 3
> > +
> > +[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
> > +[40Dh 1037 1] Length : 0A
> > +[40Eh 1038 1] Bus : 00
> > +[40Fh 1039 1] Source : 09
> > +[410h 1040 4] Interrupt : 00000009
> > +[414h 1044 2] Flags (decoded below) : 000D
> > + Polarity : 1
> > + Trigger Mode : 3
> > +
> > +[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
> > +[417h 1047 1] Length : 0A
> > +[418h 1048 1] Bus : 00
> > +[419h 1049 1] Source : 0A
> > +[41Ah 1050 4] Interrupt : 0000000A
> > +[41Eh 1054 2] Flags (decoded below) : 000D
> > + Polarity : 1
> > + Trigger Mode : 3
> > +
> > +[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
> > +[421h 1057 1] Length : 0A
> > +[422h 1058 1] Bus : 00
> > +[423h 1059 1] Source : 0B
> > +[424h 1060 4] Interrupt : 0000000B
> > +[428h 1064 2] Flags (decoded below) : 000D
> > + Polarity : 1
> > + Trigger Mode : 3
> > +
> > +[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
> > +[42Bh 1067 1] Length : 06
> > +[42Ch 1068 1] Processor ID : FF
> > +[42Dh 1069 2] Flags (decoded below) : 0000
> > + Polarity : 0
> > + Trigger Mode : 0
> > +[42Fh 1071 1] Interrupt Input LINT : 01
> > +
> > ...
> >
> > DSDT:
> >
> > +/*
> > + * Intel ACPI Component Architecture
> > + * AML/ASL+ Disassembler version 20200925 (64-bit version)
> > + * Copyright (c) 2000 - 2020 Intel Corporation
> > + *
> > + * Disassembling to symbolic ASL+ operators
> > + *
> > + * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
> > + *
> > + * Original Table Header:
> > + * Signature "DSDT"
> > + * Length 0x0000489D (18589)
> > + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
> > + * Checksum 0xDB
> > + * OEM ID "BOCHS "
> > + * OEM Table ID "BXPC "
> > + * OEM Revision 0x00000001 (1)
> > + * Compiler ID "BXPC"
> > + * Compiler Version 0x00000001 (1)
> > + */
> > +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
> > +{
> > + Scope (\)
> > + {
> > + OperationRegion (DBG, SystemIO, 0x0402, One)
> > + Field (DBG, ByteAcc, NoLock, Preserve)
> > + {
> > + DBGB, 8
> > + }
> > +
> > + Method (DBUG, 1, NotSerialized)
> > + {
> > + ToHexString (Arg0, Local0)
> > + ToBuffer (Local0, Local0)
> > + Local1 = (SizeOf (Local0) - One)
> > + Local2 = Zero
> > + While ((Local2 < Local1))
> > + {
> > + DBGB = DerefOf (Local0 [Local2])
> > + Local2++
> > + }
> > +
> > + DBGB = 0x0A
> > + }
> > + }
> > +
> >
> > [snip]
> >
> > +
> > + Processor (C000, 0x00, 0x00000000, 0x00)
> > + {
> > + Method (_STA, 0, Serialized) // _STA: Status
> > + {
> > + Return (CSTA (Zero))
> > + }
> > +
> > + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
> > + {
> > + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
> > + })
> > + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
> > + {
> > + COST (Zero, Arg0, Arg1, Arg2)
> > + }
> > + }
> > +
> > + Processor (C001, 0x01, 0x00000000, 0x00)
> > + {
> > + Method (_STA, 0, Serialized) // _STA: Status
> > + {
> > + Return (CSTA (One))
> > + }
> > +
> > + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
> > + {
> > + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
> > + })
> > + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
> > + {
> > + CEJ0 (One)
> > + }
> > +
> > + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
> > + {
> > + COST (One, Arg0, Arg1, Arg2)
> > + }
> > + }
> >
> > [snip]
> >
> > + Processor (C077, 0x77, 0x00000000, 0x00)
> > + {
> > + Method (_STA, 0, Serialized) // _STA: Status
> > + {
> > + Return (CSTA (0x77))
> > + }
> > +
> > + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
> > + {
> > + 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w.....
> > + })
> > + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
> > + {
> > + CEJ0 (0x77)
> > + }
> > +
> > + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
> > + {
> > + COST (0x77, Arg0, Arg1, Arg2)
> > + }
> > + }
> > + }
> > + }
> > +
> > ...
> >
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > ---
> > tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
> > tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
> > tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
> > tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
> > 4 files changed, 3 deletions(-)
> >
> > diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count
> > index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ab60a6ef065d8ce53ae93d311d3777d2d4afb9f6 100644
> > GIT binary patch
> > literal 1072
> > zcmXxjX)mKu7{>9_YU}A{8~a-OZpzsAwwBgf>(n~-!C>rL5ClOG1VQjwyzxDJ5<E};
> > zagzJ~UFYQFB<IC#bGsZ?jSxO>_Ev|p!(#Wi9Ts`1gb+$r6yp8Et0V-fRH#;?j|Meb
> > z)ap<tp|2h#1L{p^Fr(2AO#x^QM86>P55|BH3=GAfaQqR0!I2mejiE6Z7K`EDe+elf
> > zo_%BjMkQf%GRCA}Y#PR;qa_35voIkW6LT=hipjZ{l834Jm{x%4g_u!{nI)K2irM9u
> > zQ-MD#(OQkUHq5i*uNus+#ezC4bYhVUiyN?{2}_%?tOd*6SkZ=+?O4@`)m>=oM!N?c
> > zJy_F=wf$H(fc1mu975MHHjH577&eV#^8~g`V(S#Tr?G7Y+h?(34m;<uYXQ3#@%J)%
> > zR<LIkd)KjV1N%2|U<(Jg@y`wp?c(qrj_l*;0gfGd$3+@H!ii)2dxDdvICX~8=lJge
> > zXD)H}3g@oz{|(OH;=&y+-s92(E<fVR6Rtkv+KZyfr1aMhrK=5cDM3kEt*lu|di{4Y
> > Q$QL*>8of!Q`;?#f0%hq@0RR91
> >
> > literal 0
> > HcmV?d00001
> >
> > diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count
> > index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..edc23198cdb47a981bcbc82bc8e392b815abb554 100644
> > GIT binary patch
> > literal 18589
> > zcmb81No*V0c804+N}`ICL`n1{%eE}fGfB;!$s#FI5@m{%JW)2O!M5a)9%Q$><G@xY
> > z{kn}Lc-?y4cnR_XbwdxxE&&2$nHb0>+4U|Byj2$2yloJ?UOnfWdvDb}b*~J>UQquj
> > zp7Wh^io+pqT{B%yPyZ%o80PO%m+V}*Cv~-G_rO2XFbvfAH<Ay`8kN`S)M(WV`2uF;
> > zO^9i@Nd=?F)2W$J^VdtY?`pMYzo?mWbz}aA$hY%z_0PYo%^T>nGGDhW6p``HYB^P{
> > ztmfN_c0LxY=JM%q@<%HetlC`pgVmXQ+K5gxRWFt8z}tI<oxT!ZpKMrLYVWinmBR1(
> > z{;;R};&)e`CEuO<&)aYBSpjfJz~3PJ?W^NW?X#M-yS5(rW^LJgh2iYJ_<H9zYwT`*
> > zEQ0scYk1`QFh7K-_{P2Hcta*#F0`x<uH7~2?S9j!t#^IH3;1#9KmNNs@M+=eZND$<
> > z_&2+-QCn~NcG>c6)auroFKdPY2fEkpT21wi2A|Pl)Zi@KH;lRZ9KW-&I-D*gZPs~9
> > zak3b*V{rqzFO}Q(Slz$aW*A{S<@oO(-@kwVuUs0DmquhFdJ<0_p18{EqFtUgL+`>?
> > zu<|B?h7HGOdf+DAQ+Zv^jKM?o?_nzdj};nrDwY|8J5rN{k{SAuhoNDoCT9vg#eDi|
> > zPsL14*yBd@K+(>O`6~O+djGz@gdX*m=CXl|${{?wVMLE5A!ai#WYzJeCVXqrRCAG?
> > z&vfHQolrPyn1r1`xG{}+co<%-%^Pd;VK_JMjaPH#+^e~lrqv`*@cIGI*;fGddHyg2
> > zi+MY1M8j41Yu1<0imYBX@%%>Y-?Qgtu{2%m7=QY@BNPZhu8GO<jKQ@DI%{-<@wnv!
> > zW7IMHVC0OBmH^ZT4<q*z7Dj<%E5DD$fvaO;B=DK9k41v7urShb^%*P@Tv;TT7zx!d
> > zUq6d<D)1W^>A3oNB)GCjFfr1}5@3-|1pyZ6xCVHnQ#_co&jwGQ4J^`eZQzkk@nF(E
> > z8$EqCvPj3Z(c34Ow9h6_pG}@Vo4kF3N&5_X`V4yd40`(nllIx{>9g6>XS26YFlnEb
> > zr%%h%r{(PvOxkD2(`U%jXUN+pn6%HZr_Zpb&#<>oFlnDHo<3VVeYSY}1e5mJ>glu9
> > z(`T!<PcUhpZJs{cJbku#`vjBr8S(TP@$?z-_6a8Kv)$8YyQj}~Z=Yb&K07>pc6j>i
> > z@b(EN?X%O<XQ!vnPH&%J(mtb}KBJyKquxHjq<wDj^tr{;=N50DVA4Lfdivbz>2s^M
> > zPcUhpFvj?M7JFCP=IL{rw@)x>pW8isZuj)L-P<Raw9g$ZGAZ5(cd*Emc(dEVBW-D7
> > zWLo%kc_O<!kzL+MFlppYPvlNd<W6rSm^8B66WQ&F?Dj^2Nh5c8B6oQrcX=bhq>;N>
> > zr1KuXn?*YB@w<7X^TrJ(Mmm#Zk0<9IPtHBwoM7^tK^UM(GC)Vmc}UHMsR<eqivbD-
> > zq~(Sm3@0fJQ0~W`M5cjJPJJdM<*x1k1=DE_1}OJ+1}JgG0m@z70SYEm;|x&lD=f?j
> > zRA*vhq;tk_fPx7XF<%&<+*eqlM;3_#l)E}6?Gpwl$FfKmpu`miD45Pv!~qJX(<cm2
> > z?#m)!fD%_6pxl+^!~qJX(<cm2?#m)!fD%_6pxl*3;s6EH=@SMh_hpeVK#403Q0~ei
> > zae#v9Jf1K>xi5=^0ZLqPfO1zBi31c&r%xE5+?Ped041(CK)EZ6!~qJX(<cm2?#m)!
> > zfD%_6pxl*3;s6EH=@SMh_hpeVK#403Q0~eiae#v9^a%r$`?5$Fpu`miD0gL%I6%R4
> > z`h)?>eOV+7P~wUMl)JJ>9H3x2eZm0czAO?3C~?IB%3WC`4p1<iK4E}zUls`il(^ym
> > z<*qCe2Pl|MpD;kVFN=f$N?dV(a#t3K0~AcBPZ*%wmqo$=C9XI?xhspr0SczmCk#;T
> > z%OYWb5?36c+?7S*00q<O69y>vWsxvIi7O6J?#d!@fP(4t2?Lb-vPc-9#1#i9cV&?{
> > zK*4nSgaOKZStJZl;)(;5yRt|epkO+E!T{yIED{DNam4}3U0Ea!P%xc7VSsX976}8C
> > zxZ(iit}GG<D40&4FhIc~0~9PeK*6K~6ihNeNhAzV5{UzpMB)G?kuX3>Bn(gzi35~G
> > z;s7O)FhEHp3{Vn@1C&JK040$yKuIJFP!fp)ltkhHC6O>d!Ezp57@%OmBgRf94p1=R
> > zVQ@^0bj~ddP_UeH3j-7^=iK4|1=BgVI6%RKHIS|<j8J1eyvDw)Zr~Tv?;G(?GTND+
> > zg75$9&7WDXmy8XodBX}t`}0$FsTsy@Dc0U<g}!Pun%PpqOXDpbvl`$wU;k{$YBNv)
> > zs1&QLPBg)sPdY0x;Wobh5`@&{_N`XuSFJ{~A10Im@4*JVn;I{TXj`>BoisMEgkotb
> > z8Evno^JU`|YU?#S(uNBf=wX+by{%d<mCd(Hq6SQl$3^y(lHL4>>?x8x#j>ZMKAJrh
> > z-8_4$vRc62`C1IDLW$lj-$$gkNqU>5x0Uqv2h!UjeOhVWf)%j;_qk7#^l6qpt)x$X
> > zAbnb-%GACW#o(q~xujFLX{f%F-XKC7m0_=xmbl0M7QXO;BX52VkE^rLF}#*aup
> > zO45(A^rK4p(GR2_73p(o`lgRapCjpWEPYN%pZh@i9HbB6+mV_+!qYo%9`MlsUhaHx
> > z(t9l0$X@dB2Vd6$r@oA>b}tS-FK9S^Y*U=}y6o`c;6sFl<Ht6|X|J<RFAhFgXgGds
> > zQ=Im?iF$GHaYMuLW1Hf%*TEJq4nBiuIDTwXoc6rl>czna6Aj0YZHm*Lr`x<Z__U(o
> > z_%SaoQV8<p|4cAf%uG8^KNH^aaM8c=I#--781Tva$3KP)Sh|j&-FZ1PneHi;($${m
> > zAe%gOJW{LUp}9|MR;0Eb{(7xutkqyWcEeb2{d#TA_|;t4_^<zM*nr^(BMq0=+pX3w
> > z;428i4fwJK3+mD8XpujTElInWkHunxM&zr1@$njS*6b<2v*2DVWy(&u7Q9J7xh-~a
> > zrYHC4S^fUXot`JRo<3T6vT*CEQ8De}#JG6Xv{=@t`BV6(uo->{?ZNvxEZYARw!)P+
> > zhtWtHJ$5lOY1;Y8vT2tJmrYoDkKs+$H2k(*NW=1e2YUMLa%Q3j+|$YF9$2@|Pv(Pl
> > z0}obKzxXHLEW0!S74a%XKk*pW!7r>dL^Idz>FhP%y0x}sd|^Yk%P38h@#Xc<+LGl%
> > zo#5J!x{vDs>VB>pP!Dk3h<cFgCe%Y*2T>1m-HdvKYYTOf>k#S`*J0E)*Da{iT(_dm
> > zaNUMF%XI{F9LmR<+fj@9J5Y=IJ5h`Jqo_swTTqMox1tvHZ$mBW-;P?;zXP?XzYDdf
> > ze<x~De>ZAT|1Q*`{@tiW{d-W0`g=epME!eFi~4&}i~9GW7WMB(E$TmjTGW3KwW$9P
> > zYEl1T)S~_)s73upQH%PIp%(QYM=k0<fm+mm61AxR6lzg_40NBUKaN_|pFl0@??Wx>
> > z??)}_A3!bYA4DzcA3`naA4V<eA3-hZKaE<{e+IRv|14@z|2fp6{`06s{TEP+`Y(d+
> > z7xgDmi~3WjMg2BvQGXh>s6T^R)SpEy>K{cd>d&DT_2*HG`o~a<`o~d=`X^9}`U|K<
> > z{gbFg{g+US`ir0kMEz5!Mg1kzqW&^!QU5e*QU45TQU7JsqW&wWMg3P%i~6sj7WH38
> > zE$XkJ7WL1f7WLmiE$Y9CTGU@fE$Xj<9u)P@p%(SeqZaiqpceHnq89bvLM`gQjat-y
> > z2eqhw3ALzy8MUbYE^1N#J=CK9`=~|z4^WHxAEFlZKSC|)uY(>E^*=@}>VJY-)c+K<
> > zsQ(#iQU3~RQU7z)qW%}ChnAzcM!1-pY_9B^Jr$tS2d4^Nja3iB1gPWn={5BZoGW#!
> > z4X(m!_e_j$)S`t3oHZYp$W&24*pwd~-D;QZ$>0at2-=gGD;>V~bz`A!F8+||SX(sf
> > z#$w&9)s49y3gKU_)y!`ftWTh``huF1b*vtQQMtbDTlFXm%Z1;rH?PfE?;+1`>zm!b
> > zzF#|aIF0KIUt*DS#>yO&_5INLfab>LHH_2+%U{>d4BQEED+{<AA`{@-ArLrkEZ`Vk
> > zfCQEJ=FMp=sApw<^YdJ2wl9^Z!yh=$n?GGNKAgPz@+Rk|Zu!)s=z3Q@2&Z||>MEZP
> > z!_bc5hb{vzw!;%UxPeb^_*ha%PPd1wpaJX2xJnUih5a7WA#BE2TE1KPJQIM>I9tH*
> > zgu>#08)}*?G*lHInqnrwm<*FcOad+lV2&190e;JOIX)lbgk6s1gRfFfJ(f?B`rrz?
> > zN`g<XF3BHINq$Q5OHx04231M$-P<Jv8dOq%k^+)6fXg#VckngZB{ejvqy|cAkfcGl
> > zprDfA!>&te4639?N@|p(A-KSxlHkj&OKM_EQ}C2<9yzOtlA0uG7@i<13APKlq@bnN
> > z6r`k}B#p37|K4XoGa)szoj0_mW=d+7q$DneDQDawB&$WO$)Y4nl2W*&rjSB}6lzsT
> > zAxa8Kk_}&*R8p9b!V#4erlhbWrQrgGN@^jbmUflYLP;%>lz|HxDyfx_T02xyD<!o`
> > zQWh?7s3iDa=ROPCqAID4lG<ESJcg?p${B}s50@0#qLLz%6p^GjE?y`kSn_a5?ORn+
> > zJ0-PCQUcd46cVg<xTKElDyf5#IwYwNmn;+#EOfY}&K)YLlae|msUKG>6cVg)xTI*8
> > zN{UiaRFVd8p+X_S@`g*=(yfxVP|_Aj8pJgUg#;@bE@|s7m9&+Two1|vE>9>VSk!Py
> > z+jgs@ZIrZ4l7``ei%Qx~NZZ*~O8Ty{oszao(g<9DQAs-pX~$l*rX7^DLz0rPqd_Hg
> > z5mHyLO6sDdE=fwk1savKlaO}qS4lf5X{RLFaKT0;brVwe0hQEEN!^l^h6^|<X%`{w
> > zI;fI%QPM6+%D@F3m9(3Xb{|$ryD4e6BxT_Ok4oA@NPCW`q&<|h$0a3VJvym}ka~`)
> > zq#jD@k)-%uowS#b_8wPBdnswJBqe%vQZFI(o={1>l+-IpefxCMK0?}eQYG!9q<xaq
> > zzh5WqC#3x`m9(Fd_Dj;h0iAS!kPfg<q4X7efRYYK(%?azbdZn^Ce)e^Qqn<58akwt
> > z4iVC!ewB2Hk`77I@L`>Fn2-(+sHDS`bXbx`j_9N#gmh$3B^{xpBa)Ons*{cq($Qg+
> > zbd-{gN>b{WPC7<N$3|4rF-kfnN%nD_bexcmpH@l7De1T*rBCRj6NGf)tV%jTNhc&J
> > zb5bXrB&3t)RMJUGIw?unQ#$DsA)Pv}l1@?5DVNkIzRr2ROTk8dcXGxqs-zet#Uv>n
> > z*K3LsQaq`W;*=DZq(nj|B?u{zQb`F)N=Q;)pHAu{q`tID>Z7DSN$T&{N&SS>pHWHu
> > zl+-Ut0|Po~fRF~@S^<2NA>XA2C}}{F1_yQ0AR!IrRMH?N4NB6`kWLyRq@lb@8lt2j
> > zNg5v3NyCIRJf@O{DQQ@eMn-hf2qBG3sH71}8j+;rX`OVMkWLp=(rHRMElH^}I_V4{
> > zotacgXDI26B-v+m(pf?}TU1GBDe0^vrO)Z4bA)tmN+q46q;ry#Ij@t>6VmyTN;*$T
> > z=Orn7K_^`xqzlt3=>jEPa7q2Ki#q8dAzhqNNf#;Uq9nzWItebByYF<#%PJ{JNl8gc
> > zq;wKoEq6(&t11aMvAF9`DM{+HbrM`CcS-g&m4y3IT#_wG{b`*9*T`K``npQOttBog
> > zElC3zodlOvT~cONCE+d+mz0sD!K_Y#E8{LHdqXARh7XsNm879jodg%fUDD`Hm4tgY
> > zT+*l{4d-+cTn~3ixtdDCZ5S>oCrKlDos=h}{G3Y4Q&L`%l4Ck)jF86WRnizGjY(2!
> > zTqlha()glE8mFXjNwOz&(gYz*+)_yslr$kp>4HvzjRWo(FWgp11xhMNQf5*oO%l@N
> > zl1iGSq)AE2UeZaI2<g(YO1eZzmt4|7tf-TUgjBq%l8Tg6l%)8SPMRX5Dfl0A-p>V7
> > zlr$wtiIPq#5mM=aN-9xONs{`?ItjKUxQ|`=p-L)KQdyGvr*#tS7;#C{b(J(tNz;-v
> > zFr$-Z2x;cAN}8dh8A%$vtdlMi(&Z;A=`tl<mZYI8I_U}_U3sRGu29kyNgBSYldcld
> > z)fJU=m6EPX(#SQPbd8X%Jy%KBDCwFcC9mtG>x6Xu6P0wGlCDcqs-lxBgj9K{k}8x`
> > zktBOoC(RPl?58SemXc;ADSbmH-5{hJf1;9ZP|^)a%G}gRHwo$HE0uJUl5R>;wyKk=
> > zgjD@gl~kpqs!JM-)pSygkZP}0QjL;ok`$lQNpplW_eLenQPP|wCFXU~JR!}ms-$^J
> > znwO-$1)a1&NDF_ak`^dwL6Z6xb<!dsE&jPmTBM{!NgBANlWq~xtuIv4ElRp2NrSg_
> > z(rrSz{iRB}O-Z*UY3Pnlx<g2JzEVkdDCv$Q4KL}WB|=(ytCE%|X-SesmUYrHAua!f
> > zN?N9*Wl2ij)k${=>F!^uq`Q=KSCUfqbkaRSy7yNq=^iEBlO+4TPP$J>_kXF9?o-lz
> > zNlHJ^Ne>9=!PhG30VO?<q|8H|^pKDqexs5eQqn_7%0ALbj|l0}uT;__N_ymyhGKP{
> > zR41hRw<@VlNp(qzKh{Z)3F+~7D(NvLJ(i@z6P@&gke>WnB|V{}Cz90nR3|+pq^Eza
> > zlAco1Q%UN7rjwo#(zCx&NzW+hnIsLY=%f`wTKQX*v_eTMk~H{SCp{;m=f6=&&nfA-
> > zBn`dLNiPWL#owu<7nJk@NYS0JX%;pBS2MAMA-4MB23p*=6e(=sJ8Ic4L9p$^V<GFG
> > zzicsl{4)D{OmB{wKZkz~n?X2khS|=LKfv8Thh4h`emKG~{)hdn2fH8tAI<ys{Gz{M
> > z_zcevegxq+E&hS^Wf*_&x#u1H638F<J@3xHg*9)UP52tvEB+t`-zwo8HE?eY>~pTH
> > z+5zYj7HQ$vR@iTjBw?d7-@}Z@$>wF)o;{tkU;_efm}Z-odm4KhP5AYZ%Ia94m@C4!
> > z0v!S;X_Jl6I_q8dUD(_X8?TSdLi%!FwWBd$LhYdYs~y3B<+EU;4p;+t54I6GBOiv!
> > z>dEXC8<qpGfT>Jj26h%D&|9fE(hzCD?beaZ&RN_*7b$e%qgYuDm18mZOq5KQpqr!R
> > z*f2NX5i<?AvR#g+4ftIX5D7>0p@7b#<*anxgB!W?r753Pv%(QOz>-wnoId5pH0X)<
> > zn)v^l;QwMxrSQhan{?2CZR}GS)LFb4#hYBPvf4kMN<%UH$8h|xp9p(`?G5-SY`3<I
> > znl+<lnDBI4G#24+ua7;d`wN$5+^9CV%1@$#RzolTXiQ}_F;Sd`Rdvn|!1;o$>#&E4
> > z_(rUjQS%f3C;nit_cbFY>`MhVrUAS+kNMgEv)>5zMp(>&(zNYX6M{TgJVV!wx?u);
> > k4HL_0D`%79y!#9|m3SZ}4*20fB#f^~_-_Ll_+6a;1CLN!@c;k-
> >
> > literal 0
> > HcmV?d00001
> >
> > diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count
> > index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
> > GIT binary patch
> > literal 244
> > zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
> > z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
> > YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
> >
> > literal 0
> > HcmV?d00001
> >
> > diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
> > index 0ce6f8fc72ee..dfb8523c8bf4 100644
> > --- a/tests/qtest/bios-tables-test-allowed-diff.h
> > +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> > @@ -1,4 +1 @@
> > /* List of comma-separated changed AML files to ignore */
> > -"tests/data/acpi/q35/APIC.type4-count",
> > -"tests/data/acpi/q35/DSDT.type4-count",
> > -"tests/data/acpi/q35/FACP.type4-count",
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2
2023-09-19 7:12 ` Zhao Liu
@ 2023-09-19 8:01 ` Igor Mammedov
0 siblings, 0 replies; 38+ messages in thread
From: Igor Mammedov @ 2023-09-19 8:01 UTC (permalink / raw)
To: Zhao Liu
Cc: Michael S . Tsirkin, Ani Sinha, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, qemu-devel,
Michael Tokarev, Zhenyu Wang, Zhao Liu
On Tue, 19 Sep 2023 15:12:13 +0800
Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> Hi Igor,
>
> On Fri, Sep 15, 2023 at 03:29:07PM +0200, Igor Mammedov wrote:
> > Date: Fri, 15 Sep 2023 15:29:07 +0200
> > From: Igor Mammedov <imammedo@redhat.com>
> > Subject: Re: [PATCH 15/16] tests: bios-tables-test: Add test for smbios
> > type4 thread count2
> > X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu)
> >
> > On Fri, 25 Aug 2023 11:36:18 +0800
> > Zhao Liu <zhao1.liu@linux.intel.com> wrote:
> >
> > > From: Zhao Liu <zhao1.liu@intel.com>
> > >
> > > This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
> > > type4").
> > >
> > > Add this test to cover 2 cases:
> > > 1. Test thread count2 field with multiple sockets and multiple dies to
> > > confirm this field could correctly calculate threads per sockets.
> > >
> > > 2. Confirm that field calculation could correctly recognize the
> > > difference between "-smp maxcpus" and "-smp cpus".
> > >
> > > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > > ---
> > > tests/qtest/bios-tables-test.c | 33 +++++++++++++++++++++++++++++++++
> > > 1 file changed, 33 insertions(+)
> > >
> > > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> > > index 26474d376633..1b0c27e95d26 100644
> > > --- a/tests/qtest/bios-tables-test.c
> > > +++ b/tests/qtest/bios-tables-test.c
> > > @@ -96,6 +96,7 @@ typedef struct {
> > > uint8_t smbios_core_count;
> > > uint16_t smbios_core_count2;
> > > uint8_t smbios_thread_count;
> > > + uint16_t smbios_thread_count2;
> > > uint8_t *required_struct_types;
> > > int required_struct_types_len;
> > > int type4_count;
> > > @@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > > uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
> > > uint16_t speed, expected_speed[2];
> > > uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
> > > + uint16_t thread_count2, expected_thread_count2 = data->smbios_thread_count2;
> > > int offset[2];
> > > int i;
> > >
> > > @@ -673,6 +675,8 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > > }
> > >
> > > if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
> > > + uint64_t thread_count2_addr;
> > > +
> > > core_count2 = qtest_readw(data->qts,
> > > addr + offsetof(struct smbios_type_4, core_count2));
> > >
> > > @@ -680,6 +684,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
> > > if (expected_core_count == 0xFF && expected_core_count2) {
> > > g_assert_cmpuint(core_count2, ==, expected_core_count2);
> > > }
> > > +
> > > + thread_count2_addr = addr +
> > > + offsetof(struct smbios_type_4, thread_count2);
> > > + thread_count2 = qtest_readw(data->qts, thread_count2_addr);
> >
> > I'd mimic the same code style as used for core_count2 and avoid introducing an extra variable
>
> I'm not sure about the style of this case, since the code line is still
> too long, so which style should I pick? ;-)
>
> thread_count2 = qtest_readw(data->qts,
> addr + offsetof(struct smbios_type_4,
> thread_count2));
>
> or,
> thread_count2 = qtest_readw(data->qts,
> addr + offsetof(struct smbios_type_4,
> thread_count2));
this one
>
>
> >
> > > +
> > > + /* Thread Count has reached its limit, checking Thread Count 2 */
> > > + if (expected_thread_count == 0xFF && expected_thread_count2) {
> > > + g_assert_cmpuint(thread_count2, ==, expected_thread_count2);
> > > + }
> > > }
> > > }
> > >
> > > @@ -1050,6 +1063,7 @@ static void test_acpi_q35_tcg_thread_count(void)
> > > .required_struct_types = base_required_struct_types,
> > > .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > > .smbios_thread_count = 27,
> > > + .smbios_thread_count2 = 27,
> > > };
> > >
> > > test_acpi_one("-machine smbios-entry-point-type=64 "
> > > @@ -1058,6 +1072,23 @@ static void test_acpi_q35_tcg_thread_count(void)
> > > free_test_data(&data);
> > > }
> > >
> > > +static void test_acpi_q35_tcg_thread_count2(void)
> > > +{
> > > + test_data data = {
> > > + .machine = MACHINE_Q35,
> > > + .variant = ".thread-count2",
> > > + .required_struct_types = base_required_struct_types,
> > > + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> > > + .smbios_thread_count = 0xFF,
> > > + .smbios_thread_count2 = 260,
> > > + };
> > > +
> > > + test_acpi_one("-machine smbios-entry-point-type=64 "
> > > + "-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2",
> > > + &data);
> >
> > explain in commit message why abive -smp ==
>
> Ok, this is used to test if we could correctly distinguish smp.cpus and smp.maxcpus.
>
> Thanks,
> Zhao
>
> > > + .smbios_thread_count = 0xFF,
> > > + .smbios_thread_count2 = 260,
> >
> >
> > > + free_test_data(&data);
> > > +}
> > > +
> > > static void test_acpi_q35_tcg_bridge(void)
> > > {
> > > test_data data = {};
> > > @@ -2216,6 +2247,8 @@ int main(int argc, char *argv[])
> > > test_acpi_q35_tcg_core_count2);
> > > qtest_add_func("acpi/q35/thread-count",
> > > test_acpi_q35_tcg_thread_count);
> > > + qtest_add_func("acpi/q35/thread-count2",
> > > + test_acpi_q35_tcg_thread_count2);
> > > }
> > > qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
> > > #ifdef CONFIG_POSIX
> >
>
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2023-09-19 8:01 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-25 3:36 [PATCH 00/16] tests: Add CPU topology related smbios test cases Zhao Liu
2023-08-25 3:36 ` [PATCH 01/16] tests: test-smp-parse: Add the test for cores/threads per socket helpers Zhao Liu
2023-09-15 12:31 ` Igor Mammedov
2023-09-19 7:18 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 02/16] tests: bios-tables-test: Prepare the ACPI table change for type4 count test Zhao Liu
2023-08-25 3:36 ` [PATCH 03/16] tests: bios-tables-test: Add test for smbios type4 count Zhao Liu
2023-09-15 12:54 ` Igor Mammedov
2023-09-19 7:20 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 04/16] tests: bios-tables-test: Add ACPI table binaries for type4 count test Zhao Liu
2023-09-15 13:05 ` Igor Mammedov
2023-09-19 7:26 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 05/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core " Zhao Liu
2023-08-25 3:36 ` [PATCH 06/16] tests: bios-tables-test: Add test for smbios type4 core count Zhao Liu
2023-09-15 13:03 ` Igor Mammedov
2023-09-19 7:21 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 07/16] tests: bios-tables-test: Add ACPI table binaries for type4 core count test Zhao Liu
2023-08-25 3:36 ` [PATCH 08/16] tests: bios-tables-test: Prepare the ACPI table change for type4 core count2 test Zhao Liu
2023-08-25 3:36 ` [PATCH 09/16] tests: bios-tables-test: Extend core count2 test to cover general topology Zhao Liu
2023-09-15 13:11 ` Igor Mammedov
2023-09-19 7:14 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 10/16] tests: bios-tables-test: Update ACPI table binaries for core count2 test Zhao Liu
2023-08-25 3:36 ` [PATCH 11/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count test Zhao Liu
2023-08-25 3:36 ` [PATCH 12/16] tests: bios-tables-test: Add test for smbios type4 thread count Zhao Liu
2023-09-15 13:19 ` Igor Mammedov
2023-09-19 7:13 ` Zhao Liu
2023-08-25 3:36 ` [PATCH 13/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count test Zhao Liu
2023-08-25 3:36 ` [PATCH 14/16] tests: bios-tables-test: Prepare the ACPI table change for type4 thread count2 test Zhao Liu
2023-08-25 3:36 ` [PATCH 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2 Zhao Liu
2023-09-15 13:29 ` Igor Mammedov
2023-09-19 7:12 ` Zhao Liu
2023-09-19 8:01 ` Igor Mammedov
2023-08-25 3:36 ` [PATCH 16/16] tests: bios-tables-test: Add ACPI table binaries for type4 thread count2 test Zhao Liu
2023-09-01 9:55 ` [PATCH 00/16] tests: Add CPU topology related smbios test cases Michael Tokarev
2023-09-05 6:56 ` Zhao Liu
2023-09-15 13:48 ` Michael S. Tsirkin
2023-09-15 14:30 ` Igor Mammedov
2023-09-19 6:46 ` Zhao Liu
2023-09-06 14:40 ` Philippe Mathieu-Daudé
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