From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Radoslaw Biernacki <rad@semihalf.com>
Subject: [PATCH 0/2] target/arm: Implement Neoverse-N2
Date: Fri, 15 Sep 2023 19:54:51 +0100 [thread overview]
Message-ID: <20230915185453.1871167-1-peter.maydell@linaro.org> (raw)
This patchset implements a model of the Neoverse-N2 CPU.
Because it's very similar to the Cortex-A710 we don't
need to implement any new features for it; but because it
supports 48 bit physical addresses we can use it in the
sbsa-ref board.
Patch 1 fixes a few minor errors in the A710 definition
that I spotted while I was cross-checking it against the
N2 TRM to see what had changed.
Patch 2 is the new CPU model.
thanks
-- PMM
Peter Maydell (2):
target/arm: Correct minor errors in Cortex-A710 definition
target/arm: Implement Neoverse N2 CPU model
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
target/arm/tcg/cpu64.c | 114 ++++++++++++++++++++++++++++++++++++++-
4 files changed, 115 insertions(+), 2 deletions(-)
--
2.34.1
next reply other threads:[~2023-09-15 18:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-15 18:54 Peter Maydell [this message]
2023-09-15 18:54 ` [PATCH 1/2] target/arm: Correct minor errors in Cortex-A710 definition Peter Maydell
2023-10-17 13:13 ` Alex Bennée
2023-09-15 18:54 ` [PATCH 2/2] target/arm: Implement Neoverse N2 CPU model Peter Maydell
2023-10-17 13:29 ` Alex Bennée
2023-10-17 14:24 ` Peter Maydell
2023-10-24 16:02 ` Alex Bennée
2023-09-15 20:43 ` [PATCH 0/2] target/arm: Implement Neoverse-N2 Marcin Juszkiewicz
2023-10-17 12:40 ` Peter Maydell
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